8. 1 Background ●●● ●●●● ●●●●● ●●●● Speed of accessing memory ●●0●● ●●●0 Register access in one cycle of CPU clock o Main memory access can take many cycles o Cache sits between main memory and CPU registers to accommodate a speed difference5 8.1 Background ⚫ Speed of accessing memory ⚫ Register access in one cycle of CPU clock ⚫ Main memory access can take many cycles ⚫ Cache sits between main memory and CPU registers to accommodate a speed difference