8. Main Memory ●●● ●●●● ●●●●● ●●●● ●●0●● Objectives ●●●0 ●●●● o To provide a detailed description of various ways f organizing memory hardware To discuss various memory-management techniques, including paging and segmentation o To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging
2 8. Main Memory ⚫ Objectives ⚫ To provide a detailed description of various ways of organizing memory hardware ⚫ To discuss various memory-management techniques, including paging and segmentation ⚫ To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging
●●● 8. Main Memory ●●●● ●●●●● ●●●● 8.1 Background ●●0●● ●●●● ●●●● 8.2 Swapping 8.3 Contiguous Memory Allocation o8.4 Paging 8.5 Structure of the Page Table ●86 Segmentation e8. 7 Example: The Intel Pentium
3 8. Main Memory ⚫ 8.1 Background ⚫ 8.2 Swapping ⚫ 8.3 Contiguous Memory Allocation ⚫ 8.4 Paging ⚫ 8.5 Structure of the Page Table ⚫ 8.6 Segmentation ⚫ 8.7 Example: The Intel Pentium
8. 1 Background ●●● ●●●● ●●●●● ●●●● ●●0●● Memory is central to the operation of a. ●●●● modern computer system o Main memory and registers are only storage CPU can access directl Program must be brought (from disk) into memory e Instruction-execution cycle CPU fetches an instruction from memory according to the value of the program counter o The instruction is then decoded and may cause operands to be fetch from memory After the instruction has been executed the results may be stored back in memory
4 8.1 Background ⚫ Memory is central to the operation of a modern computer system ⚫ Main memory and registers are only storage CPU can access directly ⚫ Program must be brought (from disk) into memory ⚫ Instruction-execution cycle ⚫ CPU fetches an instruction from memory according to the value of the program counter ⚫ The instruction is then decoded and may cause operands to be fetch from memory ⚫ After the instruction has been executed, the results may be stored back in memory
8. 1 Background ●●● ●●●● ●●●●● ●●●● Speed of accessing memory ●●0●● ●●●0 Register access in one cycle of CPU clock o Main memory access can take many cycles o Cache sits between main memory and CPU registers to accommodate a speed difference
5 8.1 Background ⚫ Speed of accessing memory ⚫ Register access in one cycle of CPU clock ⚫ Main memory access can take many cycles ⚫ Cache sits between main memory and CPU registers to accommodate a speed difference
8. 1 Background ●●● ●●●● ●●●●● ●●●● ●●0●● Memory address ●●●0 ●●●● e Memory consist of a larger array of words or bytes, each with its own address We do ignore how a program generates a memory address o We are interested only in the sequence of memory address
6 8.1 Background ⚫ Memory address ⚫ Memory consist of a larger array of words or bytes, each with its own address ⚫ We do ignore how a program generates a memory address ⚫ We are interested only in the sequence of memory address
8. 1 Background ●●● ●●●● ●●●●● ●●●● ●●0●● Protection of memory address ●●●● ●●●● Need to o Protect the operating system from access by user processes o Protect the user process from others o Firstly need to make sure that each process has separate memory space o Need to determine the range of legal address of process o Need to ensure that the process can access only these legal addresses
7 8.1 Background ⚫ Protection of memory address ⚫ Need to ⚫ Protect the operating system from access by user processes ⚫ Protect the user process from others ⚫ Firstly need to make sure that each process has separate memory space ⚫ Need to determine the range of legal address of process ⚫ Need to ensure that the process can access only these legal addresses
8. 1 Background ●●● ●●●● ●●●●● ●●●● o a pair of base and limit ●●0●● ▲鱼 0 registers define the operating address space system o The base register hold 256000 the smallest legal process physical memory 300040 address 300040 base ● The limit register process specifies the size of the 420940 120900 range limit o The cPu hardware process compare every address 880000 generated in user mode with the registers 1024000
8 8.1 Background ⚫ A pair of base and limit registers define the address space ⚫ The base register hold the smallest legal physical memory address ⚫ The limit register specifies the size of the range ⚫ The CPU hardware compare every address generated in user mode with the registers
8. 1 Background ●●● ●●●● ●●●●● ●●●● ●●0●● Address binding ●●●0 ●●●● The normal procedure of a process o The processes on the disk that are waiting to be brought into memory for execution form input queue Select one process in the input queue and load the process into memory It accesses instructions and data from memory o As the process terminates, its memory space is declared available
9 8.1 Background ⚫ Address binding ⚫ The normal procedure of a process ⚫ The processes on the disk that are waiting to be brought into memory for execution form input queue ⚫ Select one process in the input queue and load the process into memory ⚫ It accesses instructions and data from memory ⚫ As the process terminates, its memory space is declared available
8. 1 Background ●●● ●●●● ●●●●● ●●●● o Address may be represented in different way.080 ●●●● g Address are generally sym bolic addresses in source program E.g. goto loop1 o A com piler will typically bind these symbolic addresses to re-ocatable addresses E.g. 14: 14 bytes from the beginning of this module The linkage editor or loader will in turn bind the re locatable addresses to absolute addresses 0x00074014 Each bind is a mapping from a address space to another
10 8.1 Background ⚫ Address may be represented in different way E.g. ⚫ Address are generally symbolic addresses in source program ▪ E.g. goto loop1 ⚫ A compiler will typically bind these symbolic addresses to re-locatable addresses ▪ E.g. 14: 14 bytes from the beginning of this module ⚫ The linkage editor or loader will in turn bind the relocatable addresses to absolute addresses ▪ 0x0007 4014 Each bind is a mapping from a address space to another
●●● source ●●●● ●●●●● progre ●●●● ●●0●● ●●●● ●●●● Multi-step Processing of compiler or comple assembler tir Ime a User Program object module other module linkage editor load module time system library loader dynamically loaded system library in-memory execution dynamic binary linking time(run memory time Image
11 Multi-step Processing of a User Program
