DS12887 unaffected by the lower input voltage as vc falls below 3 yolts typical the ram and timekeeper are switched over to an internal lithium y source The timekeeping function maintains an accuracy of+l minute per month at 25C regardless of the voltage input on the Voc pin. MOT (Mode Seleet)-The MOT pin offers the flexibility to choose between two bus types.When connected to Vcc,Motorola bus timing is selected.When connected to GND or left disconnected,Intel bus timing is selected.The pin has an internal pulldown resistance of approximately 20 k. SQW(Square Wave Output)-The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the Real Time Clock.The frequency of the SQW pin can be changed by programming Register A as shown in Table 1.The SQW signal can be turned on and off using the SQWE bit in Register B.The SQW signal is not available when Vcc is less than 4.25 volts,typically. PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 1 SELECT BITS REGISTER A t PERIODIC SOW OUTPUT INTERRUPT RATE FREOUENCY 0 3.90625 256z 7.8125ms 28H☑ 122070u1s 8.192kHz 0 0 244141us 4.096kHz 488281μs 2048kH2 976.56254s 1.024kH亚 0 1.953125ms 512Hz 1 0 0 0 3.90625ms 256Hz 0 7.8125ms 128Hz 0 15.625ms 64 Hz 3125m 32H2 62. ms 16亚 125ms 8H☑ 250ms 4H2 500ms 2 Hz ADO-AD7 (Multiplexed Bidirectional Address/Data Bus)-Multiplexed buses save pins because address information and data information time-share the same signal paths.The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle.Address/data multiplexing does not slow the access time of the DS12887 since the bus change from address to data occurs during the internal RaM access time.Addresses must be valic prior to the falling edge of AS/ALE,at which time the DS12887 latches the address from AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR pulses.In a read cycle the DS12887 outputs 8 bits of data during the latter portion of the DS or RD pulses.The read cycle is terminated and the bus returns to a high impedance state as DS transitions low in the case of Motorola timing or as RD transitions high in the case of Intel timing AS(Address Strobe Input)-A positive ing address strobe pulse serves to demultiplex the bus The falling edge of AS/ALE causes the address to be latched within the DS12887.The next rising edge that 3of19 DS12887 3 of 19 unaffected by the lower input voltage. As VCC falls below 3 volts typical, the RAM and timekeeper are switched over to an internal lithium energy source. The timekeeping function maintains an accuracy of ±1 minute per month at 25°C regardless of the voltage input on the VCC pin. MOT (Mode Select) – The MOT pin offers the flexibility to choose between two bus types. When connected to VCC, Motorola bus timing is selected. When connected to GND or left disconnected, Intel bus timing is selected. The pin has an internal pulldown resistance of approximately 20 kW. SQW (Square Wave Output) – The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the Real Time Clock. The frequency of the SQW pin can be changed by programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE bit in Register B. The SQW signal is not available when VCC is less than 4.25 volts, typically. PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 1 SELECT BITS REGISTER A RS3 RS2 RS1 RS0 tPI PERIODIC INTERRUPT RATE SQW OUTPUT FREQUENCY 0 0 0 0 None None 0 0 0 1 3.90625 ms 256 Hz 0 0 1 0 7.8125 ms 128 Hz 0 0 1 1 122.070 ms 8.192 kHz 0 1 0 0 244.141 ms 4.096 kHz 0 1 0 1 488.281 ms 2.048 kHz 0 1 1 0 976.5625 ms 1.024 kHz 0 1 1 1 1.953125 ms 512 Hz 1 0 0 0 3.90625 ms 256 Hz 1 0 0 1 7.8125 ms 128 Hz 1 0 1 0 15.625 ms 64 Hz 1 0 1 1 31.25 ms 32 Hz 1 1 0 0 62.5 ms 16 Hz 1 1 0 1 125 ms 8 Hz 1 1 1 0 250 ms 4 Hz 1 1 1 1 500 ms 2 Hz AD0–AD7 (Multiplexed Bidirectional Address/Data Bus) – Multiplexed buses save pins because address information and data information time-share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS12887 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the falling edge of AS/ ALE, at which time the DS12887 latches the address from AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR pulses. In a read cycle the DS12887 outputs 8 bits of data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions low in the case of Motorola timing or as RD transitions high in the case of Intel timing. AS (Address Strobe Input) – A positive-going address strobe pulse serves to demultiplex the bus. The falling edge of AS/ALE causes the address to be latched within the DS12887. The next rising edge that