B A B D Fig. 4. Single-branch input devices. (A) linal -V characteristics of -n diodes encoded at p-Si/n-Ge(blue), p-Si/n-GaAs (red), and p-si/n-CdSe torange) branched junctions. (B)/V curve of the same p-si/n-GaAs diode on semilog scale: the slope(blue dashed line) yields an ideality factor Si/Sio2/Au branched NWs.(8)HRTEM image of Si/SiO2/Au n-Ge(@ and p-si/Sio, Au(D) branched junctions, respectively. a source drain voltage of 0.5 v was used in the measuremen ttern from the yellow square region, indexed as a superposition of [001] blue)and (-112(green) zone patterns. The marked yellow spot in the FFT attern is one of the associated double diffraction reflections, where gate electrode(Fig. 4C, Inset, and D, Inset and Fig S3B and C) b+c(C and D)SEM(O) and HRTEM(D)images of Si/Sio2/Ge branched Current (Isd)vs. branch-gate voltage(g) data recorded on NW p-Si/SiO2/n-Ge(Fig. 4C)and p-Si/Sio2/Au(Fig. 4D)branched NW FETS at a source-drain voltage of 0.5 V show a characteristic orphous layer sandwiched between crystalline Si-backbone depletion mode FET behavior(31), with a turnoff current nd branch NWs, which is consistent with our design for type 100 pA and on/off ratio 10. The calculated subthreshold II structures. Analysis of the Au branch last close to the junction slopes for these two nanoscale FEt devices are 120 and (Fig. 3B, Inset)shows the superposition of( 112)and(100) zone 150 mV/decade, respectively. The subthreshold values, which patterns and indicates the Au branch grows along the(110) indicate good gate coupling, are especially notable given that direction, the same as in Si/Au branched NWs. We note that the gate lengths for the n-Ge and Au-branch devices are only the sio, shell on these si-nw backbones can be ly extended 30 and 35 nm, respectively In addition, we have investigated additional functional proper ic layer deposition(32)and has the potential to significantly ties for synthetically encoded branch/backbone NW structures as d the scope of functionalities defined at the branched well as the incorporation of multiple functional branches. First, we have characterized the photonic properties of p-Si/n-GaAs We have fabricated and measured single-branch/backbone backbone/branch heterostructures, where the direct-band-gap NW devices to examine the potential for encoding of functional GaAs branch can yield light emission in a forward biased diode (FET Properties such as p-n diodes and field effect transistors (34). Significantly, electroluminescence(EL)data recorded from by synthesis(see Materials and Methods; Fig. S3). For a p-si/n-GaAs device(Fig 5A)exhibits highly localized emission ample, p-n diodes should be encoded at the junction of from the branch junction in forward bias, thus making these p-Si-NW backbone and n-type semiconductor branch, where we point-like, nanoscale active emitters(nanoLEDs). The EL spec- n-CdSe branches. Two-terminal electrical transport measure. responding tis tihen fraas the branch unctions was robust; that ackbone/branch NW structures(Fig 4A)all exhibit clear ated on/off cycles did not affect th rectification with threshold voltages of approximately and studies of over 20 p-Si/n-GaAs nanoLEDs yielded similar consistent with expectations for p-n diode(31). More characterization of the Si/GaAs p-n diode(Fig. 4B )yields a room We have exploited the reproducibility and robustness of the temperature ideality factor, n, of 2.4. Although the n value indi- p-si/n-GaAs nanoLEDs to study an addressable array consisting ates surface recombination in the diode(33)and suggests that of three n-GaAs Nw branches on p-Si-NW backbone(Fig 5B) further optimization could be achieved in the future, the present When a forward bias was applied to turn on one(Fig 5B, Upp sults nevertheless demonstrate our capability to independently Right ), two(Fig. 5B, Lower Left), or three(Fig 5B, Lower Right) define the doping profile of backbone and branch NWs necessary nanoLEDs sequentially, EL measurements demonstrate loca- for encoding device function lized and addressable emission only from the junctions in forward We have also examined the potential for encoding nanoscale bias. Moreover, we have assembled and characterized seven FETs in type II branched NWs, where p-Si-NW backbone serves robust nanoLEDs within a 100 x 100 um- area(Fig. S4), thu as the active semiconductor channel, the Sio, shell layer as the demonstrating the potential of this bottom-up approach for gate dielectric, and heavily doped n-Ge or Au-branch NWs as larger-scale integration of these unique photonic devices. nanoscale gate electrodes. Source and drain contacts were In addition, the concept of synthetically encoding multiple defined on p-Si-NW backbone, and an additional contact was functional branch devices has been used to investigate their made at the end of n-Ge or Au branch as voltage input for the potential as logic gates. A two branch input FETconfigured from 12214iwww.pnas.org/cgi/doi/10.1073/pnas.1108584108 Jiang et alamorphous layer sandwiched between crystalline Si-backbone and branch NWs, which is consistent with our design for type II structures. Analysis of the Au branch last close to the junction (Fig. 3B, Inset) shows the superposition of h112i and h100i zone patterns and indicates the Au branch grows along the h110i direction, the same as in Si∕Au branched NWs. We note that the SiO2 shell on these Si-NW backbones can be readily extended to other types of functional materials conformally deposited by atomic layer deposition (32) and has the potential to significantly expand the scope of functionalities defined at the branched junctions. We have fabricated and measured single-branch/backbone NW devices to examine the potential for encoding of functional device properties such as p-n diodes and field effect transistors (FETs) by synthesis (see Materials and Methods; Fig. S3). For example, p-n diodes should be encoded at the junction of p-Si-NW backbone and n-type semiconductor branch, where we have synthesized and studied structures with n-Ge, n-GaAs, and n-CdSe branches. Two-terminal electrical transport measure￾ments recorded on p-Si∕n-Ge, p-Si∕n-GaAs, and p-Si∕n-CdSe backbone/branch NW structures (Fig. 4A) all exhibit clear current rectification with threshold voltages of approximately 1.0 V, consistent with expectations for p-n diode (31). More detailed characterization of the Si∕GaAs p-n diode (Fig. 4B) yields a room temperature ideality factor, n, of 2.4. Although the n value indi￾cates surface recombination in the diode (33) and suggests that further optimization could be achieved in the future, the present results nevertheless demonstrate our capability to independently define the doping profile of backbone and branch NWs necessary for encoding device function. We have also examined the potential for encoding nanoscale FETs in type II branched NWs, where p-Si-NW backbone serves as the active semiconductor channel, the SiO2 shell layer as the gate dielectric, and heavily doped n-Ge or Au-branch NWs as nanoscale gate electrodes. Source and drain contacts were defined on p-Si-NW backbone, and an additional contact was made at the end of n-Ge or Au branch as voltage input for the gate electrode (Fig. 4 C, Inset, and D, Inset and Fig. S3 B and C). Current (Isd) vs. branch-gate voltage (Vg) data recorded on p-Si∕SiO2∕n-Ge (Fig. 4C) and p-Si∕SiO2∕Au (Fig. 4D) branched NW FETs at a source-drain voltage of 0.5 V show a characteristic depletion mode FET behavior (31), with a turnoff current < 100 pA and on/off ratio > 104. The calculated subthreshold slopes for these two nanoscale FET devices are 120 and 150 mV∕decade, respectively. The subthreshold values, which indicate good gate coupling, are especially notable given that the gate lengths for the n-Ge and Au-branch devices are only 30 and 35 nm, respectively. In addition, we have investigated additional functional proper￾ties for synthetically encoded branch/backbone NW structures as well as the incorporation of multiple functional branches. First, we have characterized the photonic properties of p-Si∕n-GaAs backbone/branch heterostructures, where the direct-band-gap GaAs branch can yield light emission in a forward biased diode (34). Significantly, electroluminescence (EL) data recorded from a p-Si∕n-GaAs device (Fig. 5A) exhibits highly localized emission from the branch junction in forward bias, thus making these point-like, nanoscale active emitters (nanoLEDs). The EL spec￾trum (Fig. 5A, Lower) exhibits a peak maximum at 860 nm, cor￾responding to the GaAs band-edge emission. We note that the localized emission from the branch junctions was robust; that is, repeated on/off cycles did not affect the emission properties, and studies of over 20 p-Si∕n-GaAs nanoLEDs yielded similar results. We have exploited the reproducibility and robustness of the p-Si/n-GaAs nanoLEDs to study an addressable array consisting of three n-GaAs NW branches on p-Si-NW backbone (Fig. 5B). When a forward bias was applied to turn on one (Fig. 5B, Upper Right), two (Fig. 5B, Lower Left), or three (Fig. 5B, Lower Right) nanoLEDs sequentially, EL measurements demonstrate loca￾lized and addressable emission only from the junctions in forward bias. Moreover, we have assembled and characterized seven robust nanoLEDs within a 100 × 100 um2 area (Fig. S4), thus demonstrating the potential of this bottom-up approach for larger-scale integration of these unique photonic devices. In addition, the concept of synthetically encoding multiple functional branch devices has been used to investigate their potential as logic gates. A two branch input FETconfigured from Fig. 3. Structural characterization of type II branched NW heterostructures. (A) SEM image of Si∕SiO2∕Au branched NWs. (B) HRTEM image of Si∕SiO2∕Au junction. The black line marks the SiO2∕Si interface. (Lower Right Inset) FFT pattern from the yellow square region, indexed as a superposition of [001] (blue) and ½−112 (green) zone patterns. The marked yellow spot in the FFT pattern is one of the associated double diffraction reflections, where a ¼ b þ c. (C and D) SEM (C) and HRTEM (D) images of Si∕SiO2∕Ge branched NW. Fig. 4. Single-branch input devices. (A) Two-terminal I–V characteristics of p-n diodes encoded at p-Si∕n-Ge (blue), p-Si∕n-GaAs (red), and p-Si∕n-CdSe (orange) branched junctions. (B) I–V curve of the same p-Si∕n-GaAs diode on semilog scale; the slope (blue dashed line) yields an ideality factor n ¼ 2.4. (C and D) I–Vg curves of nanoscale FETs encoded at p-Si∕SiO2∕ n-Ge (C) and p-Si∕SiO2∕Au (D) branched junctions, respectively. A source￾drain voltage of 0.5 V was used in the measurement. 12214 ∣ www.pnas.org/cgi/doi/10.1073/pnas.1108584108 Jiang et al.