ANC FIGURE 85.9 Example logic circuit with internal node 7 stuck at 0(7/0) TABLE 85.2 Test Pattern for Node 7/0 for the Circuit in Fig. 85.9 AB123456789101112 101010111100111good 101010110101100 with fault7/0 observation from outside the component package. In that case, it is necessary to create a condition where the value of the signal on an externally observable node, say node t, will be different for each of the two possible values that node v can take on, that is, node t shall be driven to logic state y or -y depending upon whether node v is at logic state x or -x, respectively. Note that x and y may represent the same or different logic states. The external pins of a component are the only means of applying the stimuli and observing the behavior of that component. During testing, a test pattern is used as the stimulus to detect the presence of a particular fault by causing at least one output pin of the component to take on a different value depending upon whether the targeted fault is present or not. Thus, a test pattern is used for controlling the circuits nodes so that the presence of a fault on a circuit node can be observed on at least one of the circuit's external pins. Solving the dual problems of controllability and observability is the primary objective of all test methods. The logic-to-pin ratio of a digital circuit is a relative measure of the ratio of possible faults in the circuit to the number of signal pins(i.e, not including the constant power/ground pins)of that component. A large-value logic-to-pin ratio implies that logic states of a large number of circuit nodes must be controlled using a small number of external pins. As a result, conflicting requirements for controllability and observability become harder to satisfy, and the circuit is considered to be more difficult to test Consider Fig 85.9, which depicts a single(hypothetical) integrated circuit(IC) component and shows its internal circuitry which uses four NAND gates. The nodes of the circuit are numbered 1 through 12 and the external pins of the component are labeled A, B, and C. To detect if node 7 is stuck at logic 0(i.e, 7/0), a test pattern must be found that sets node 7(and hence, node 5)to the logic l state. This can be achieved by setting either or both of the external pins A and b to the logic 0 state. Furthermore, to observe (or deduce)the value of node 7 at the only externally visible circuit pin, C, it is necessary to create a condition where the logic state of node 12 becomes dependent on the value of node 7. The only path from node 7 to node 12 passes through node 10, and since node 10 is the output of a nand gate the second input to that gate(i.e, node 6)must be set to the logic 1 state by setting input pin A to the logic 1 state. Therefore, the only possible test pattern for 7/0 is A=I and B=0. At this point, we must still continue the analysis to see if indeed node 12 will reflect the value of node 7. With input terminals A and B set to logic 1 and logic 0, respectively, node 9 will be set to logic 0, which causes node 1l to become logic 1. with these settings, the value at node 12 will be determined by the value at node 10 and the test pattern is valid. Table 85.2 shows the values of all circuit nodes when this test pattern is applied to the circuit of Fig 85.9 It should be evident from the simple example of a combinational circuit described above that test pattern generation for digital circuits can be very difficult and involved. The problem becomes much more complex when dealing with sequential circuits, where the internal state variables(ie, bistable memory storage elements such as latches and flip-flops)must be treated as pseudo-inputs and pseudo-outputs that must be controlled and bserved using the external pins of the component. In this case test patterns become test sequences that must be applied in precise order, and outputs must be observed only at prescribed times. Thus, the testing of sequential e 2000 by CRC Press LLC© 2000 by CRC Press LLC observation from outside the component package. In that case, it is necessary to create a condition where the value of the signal on an externally observable node, say node t, will be different for each of the two possible values that node v can take on, that is, node t shall be driven to logic state y or ~y depending upon whether node v is at logic state x or ~x, respectively. Note that x and y may represent the same or different logic states. The external pins of a component are the only means of applying the stimuli and observing the behavior of that component. During testing, a test pattern is used as the stimulus to detect the presence of a particular fault by causing at least one output pin of the component to take on a different value depending upon whether the targeted fault is present or not. Thus, a test pattern is used for controlling the circuit’s nodes so that the presence of a fault on a circuit node can be observed on at least one of the circuit’s external pins. Solving the dual problems of controllability and observability is the primary objective of all test methods. The logic-to-pin ratio of a digital circuit is a relative measure of the ratio of possible faults in the circuit to the number of signal pins (i.e., not including the constant power/ground pins) of that component. A large-value logic-to-pin ratio implies that logic states of a large number of circuit nodes must be controlled using a small number of external pins. As a result, conflicting requirements for controllability and observability become harder to satisfy, and the circuit is considered to be more difficult to test. Consider Fig. 85.9, which depicts a single (hypothetical) integrated circuit (IC) component and shows its internal circuitry which uses four NAND gates. The nodes of the circuit are numbered 1 through 12 and the external pins of the component are labeled A, B, and C. To detect if node 7 is stuck at logic 0 (i.e., 7/0), a test pattern must be found that sets node 7 (and hence, node 5) to the logic 1 state. This can be achieved by setting either or both of the external pins A and B to the logic 0 state. Furthermore, to observe (or deduce) the value of node 7 at the only externally visible circuit pin, C, it is necessary to create a condition where the logic state of node 12 becomes dependent on the value of node 7. The only path from node 7 to node 12 passes through node 10, and since node 10 is the output of a NAND gate the second input to that gate (i.e., node 6) must be set to the logic 1 state by setting input pin A to the logic 1 state. Therefore, the only possible test pattern for 7/0 is A = 1 and B = 0. At this point, we must still continue the analysis to see if indeed node 12 will reflect the value of node 7. With input terminals A and B set to logic 1 and logic 0, respectively, node 9 will be set to logic 0, which causes node 11 to become logic 1. With these settings, the value at node 12 will be determined by the value at node 10 and the test pattern is valid. Table 85.2 shows the values of all circuit nodes when this test pattern is applied to the circuit of Fig. 85.9. It should be evident from the simple example of a combinational circuit described above that test pattern generation for digital circuits can be very difficult and involved. The problem becomes much more complex when dealing with sequential circuits, where the internal state variables (i.e., bistable memory storage elements such as latches and flip-flops) must be treated as pseudo-inputs and pseudo-outputs that must be controlled and observed using the external pins of the component. In this case test patterns become test sequences that must be applied in precise order, and outputs must be observed only at prescribed times. Thus, the testing of sequential FIGURE 85.9 Example logic circuit with internal node 7 stuck at 0 (7/0). TABLE 85.2 Test Pattern for Node 7/0 for the Circuit in Fig. 85.9 A B 123456789 10 11 12 C 1 0 10101111 0 0 1 1 1 good circuit 1 0 101011 0 1 0 1 1 0 0 with fault 7/0