newer approaches of random testing the book by Bardell et al. contains basic information. The latest state-of- the-art research is to be found mainly in proceedings of the IEEE International Test Conference. 85.2 Design for Test Bulent I. Dervisoglu Testing of electronic circuits, which has long been pursued as an activity that follows the design and manufacture of (at least)the prototype product, has currently become a topic of up-front investigation and commitment. Today, it is not uncommon to list the design for testability(dFt) features of a product among the so-called functional requirements in the definition of a new product to be developed. Just how such a major transfor- mation has occurred can be understood by examining the testability problems faced by manufacturing orga- nizations and considering their impact on time to market(TTM) The Testability Problem The primary objective of testing digital circuits at chip, board, or system level is to detect the presence of hardware failures induced by faults in the manufacturing processes or by operating stress or wearout mecha sms. Furthermore, during manufacturing, a secondary but equally important objective is to accurately determine which component or physical element(e.g, connecting wire) is faulty so that quick diagnosis/repair of the product becomes possible. These objectives are necessary due to imperfections in the manufacturing processes used in building digital electronic components/systems. All digital circuits must undergo appropriate level testing to avoid shipping faulty components/systems to the customer. Analog circuits may have minimum and maximum allowable input signal values(e.g, input voltage)as well as infinitely many values in between these that the component has to be able to respond to. Testing of analog circuits is often achieved by checking the circuit response at the specified upper and lower bounds as well as observing/quantifying the change of the output response with varying input signal values. On the other hand, the behavior of a digital system is characterized by discrete(as opposed to continuous)responses to discrete operating state/input signal permu- tations such that testing of digital circuits may be achieved by checking their behavior under every operating de and input signal permutation. In principle this approach is valid. However, in practice, most digital ircuits are too complex to be tested using such a brute force technique. Instead, test methods have been developed to test digital circuits using only a fraction of all possible test conditions without sacrificing test coverage. Here, test coverage is used to refer to the ratio of faults that can be detected to all faults which are taken into consideration, expressed as a percentage. At the present time the most popular fault model is the so- called stuck-at fault model that refers to individual nets being considered to be fault-free (i.e. good network) or considered to be permanently stuck at either one of the logic I or logic 0 values. For example, if the device under test(DUT) contains several components(or building blocks), where the sum of all input and output terminals(nodes)of the components is k, there are said to be 2k possible stuck-at faults, corresponding to each of the circuit nodes being permanently stuck at one of the two possible logic states. In general, a larger number of possible stuck-at faults leads to increased difficulty of testing the digital circuit For the purpose of test pattern(i.e, input stimulus)generation it is often assumed that the circuit under test (CUT) is either fault-free or it contains only one node which is permanently stuck at a particular logic state Thus, the most widely used fault model is the so-called single stuck-at fault model. Using this model each fault is tested by applying a test pattern that, in a good circuit, drives the particular node to the logic state lich has the opposite value from the state of the fault assumed to be present in the faulty circuit. For example, to test if node v is stuck at logic state x(denoted by v/x or v-x), a test pattern must be used that would cause node v to be driven to the opposite of logic state x if the circuit is not faulty. Thus, the test pattern attempts to show that node v is not stuck at x by driving the node to a value other than x, which for a two-valued digital circuit must be the opposite of x(denoted by -x). This leads to the requirement that to detect any stuck-at fault wx, it is necessary to be able to control the logic value at node v so that it can be set to -v. If the signal value at node v can be observed directly by connecting it to a test equipment, the particular fault v/x can be detected readily. However, in most cases, node v may be an internal node, which is inaccessible for direct e 2000 by CRC Press LLC© 2000 by CRC Press LLC newer approaches of random testing the book by Bardell et al. contains basic information. The latest state-of￾the-art research is to be found mainly in proceedings of the IEEE International Test Conference. 85.2 Design for Test Bulent I. Dervisoglu Testing of electronic circuits, which has long been pursued as an activity that follows the design and manufacture of (at least) the prototype product, has currently become a topic of up-front investigation and commitment. Today, it is not uncommon to list the design for testability (DFT) features of a product among the so-called functional requirements in the definition of a new product to be developed. Just how such a major transfor￾mation has occurred can be understood by examining the testability problems faced by manufacturing orga￾nizations and considering their impact on time to market (TTM). The Testability Problem The primary objective of testing digital circuits at chip, board, or system level is to detect the presence of hardware failures induced by faults in the manufacturing processes or by operating stress or wearout mecha￾nisms. Furthermore, during manufacturing, a secondary but equally important objective is to accurately determine which component or physical element (e.g., connecting wire) is faulty so that quick diagnosis/repair of the product becomes possible. These objectives are necessary due to imperfections in the manufacturing processes used in building digital electronic components/systems. All digital circuits must undergo appropriate level testing to avoid shipping faulty components/systems to the customer. Analog circuits may have minimum and maximum allowable input signal values (e.g., input voltage) as well as infinitely many values in between these that the component has to be able to respond to. Testing of analog circuits is often achieved by checking the circuit response at the specified upper and lower bounds as well as observing/quantifying the change of the output response with varying input signal values. On the other hand, the behavior of a digital system is characterized by discrete (as opposed to continuous) responses to discrete operating state/input signal permu￾tations such that testing of digital circuits may be achieved by checking their behavior under every operating mode and input signal permutation. In principle this approach is valid. However, in practice, most digital circuits are too complex to be tested using such a brute force technique. Instead, test methods have been developed to test digital circuits using only a fraction of all possible test conditions without sacrificing test coverage. Here, test coverage is used to refer to the ratio of faults that can be detected to all faults which are taken into consideration, expressed as a percentage. At the present time the most popular fault model is the so￾called stuck-at fault model that refers to individual nets being considered to be fault-free (i.e., good network) or considered to be permanently stuck at either one of the logic 1 or logic 0 values. For example, if the device under test (DUT) contains several components (or building blocks), where the sum of all input and output terminals (nodes) of the components is k, there are said to be 2k possible stuck-at faults, corresponding to each of the circuit nodes being permanently stuck at one of the two possible logic states. In general, a larger number of possible stuck-at faults leads to increased difficulty of testing the digital circuit. For the purpose of test pattern (i.e., input stimulus) generation it is often assumed that the circuit under test (CUT) is either fault-free or it contains only one node which is permanently stuck at a particular logic state. Thus, the most widely used fault model is the so-called single stuck-at fault model. Using this model each fault is tested by applying a specific test pattern that, in a good circuit, drives the particular node to the logic state which has the opposite value from the state of the fault assumed to be present in the faulty circuit. For example, to test if node v is stuck at logic state x (denoted by v/x or v-x), a test pattern must be used that would cause node v to be driven to the opposite of logic state x if the circuit is not faulty. Thus, the test pattern attempts to show that node v is not stuck at x by driving the node to a value other than x, which for a two-valued digital circuit must be the opposite of x (denoted by ~x). This leads to the requirement that to detect any stuck-at fault v/x, it is necessary to be able to control the logic value at node v so that it can be set to ~v. If the signal value at node v can be observed directly by connecting it to a test equipment, the particular fault v/x can be detected readily. However, in most cases, node v may be an internal node, which is inaccessible for direct