concerned with providing access points for testing(see controllability and observability in Section 85. 2).As test pattern generation becomes even more prohibitive, probabilistic solutions based on compaction and using fault simulation are more widespread, especially if they are supported by dFt techniques and they can avoid the major expense of dedicated external testers. However, any technique chosen must be incorporated within the framework of a powerful CAD system providing semiautomatic analysis and feedback, such that the rule of ten can be kept under control: if one does not find a failure at a particular stage, then detection at the next stage will cost 10 times as much! Defining Terms Aliasing: Whenever the faulty output produces the same signature as a fault-free output. Built-in self-test(BIST): The inclusion of on-chip circuitry to provide testing Fault coverage: The fraction of possible failures that the test technique can detect. Fault simulation: An empirical method used to determine how faults affect the operation of the circuit and also how much testing is required to obtain the desired fault coverage. IpDs testing: A parametric technique to monitor the current Ipp that a circuit draws when it is in a quiescent LFSR: A shift register formed by D flip-flops and EXOR gates, chained together, with a synchronous clock, used either as input pattern generator or as signature analyzer. MISR: Multiple-input LFSR. Off-line testing: Testing process carried out while the tested circuit is not in use. On-line testing: Concurrent testing to detect errors while circuit is in operation Pseudo-random pattern generator: Generates a binary sequence of patterns where the bits appear to be random in the local sense(1 and 0 are equally likely), but they are repeatable(hence only pseudo-random). Random testing: The process of testing using a set of pseudo-randomly generated patterns Sequential fault: A fault that causes a combinational circuit to behave like a sequential one. Signature analysis: A test where the responses of a device over time are compacted into a characteristic value called a signature, which is then compared to a known good one. Stuck-at fault: A fault model represented by a signal stuck at a fixed logic value(0 or 1) est pattern(test vector): Input vector such that the faulty output is different from the fault-free output(the fault is stimulated and detected) Related Topic 23.2 Testing References M. Abramovici, M.A. Breuer and A D. Friedman, Digital Systems Testing and Testable Design, Rockville, Md: IEEE Press, 1992. P.H. Bardell, W.H. McAnney, and J Savir, Built-In Test for VLSI: Pseudorandom Techniques, New York: John K. Cattell and J.C. Muzio, Synthesis of one-dimensional linear hybrid cellular automata, IEEE Trans. Computer Aided Design, vol. 15, no. 3, Pp 325-335, 1996. N H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1993 T.W. Williams(Ed ) VLSI Testing, Amsterdam: North-Holland, 198 Further Information The author would like to recommend reading the book by abramovici et al. [ 1992] that, at the present time, gives the most comprehensive view of testing methods and design for testability. More information on deter- ministic pattern generation can also be found in Fault Tolerant Computing, edited by D K. Pradhan, and for e 2000 by CRC Press LLC© 2000 by CRC Press LLC concerned with providing access points for testing (see controllability and observability in Section 85.2). As test pattern generation becomes even more prohibitive, probabilistic solutions based on compaction and using fault simulation are more widespread, especially if they are supported by DFT techniques and they can avoid the major expense of dedicated external testers. However, any technique chosen must be incorporated within the framework of a powerful CAD system providing semiautomatic analysis and feedback, such that the rule of ten can be kept under control: if one does not find a failure at a particular stage, then detection at the next stage will cost 10 times as much! Defining Terms Aliasing: Whenever the faulty output produces the same signature as a fault-free output. Built-in self-test (BIST): The inclusion of on-chip circuitry to provide testing. Fault coverage: The fraction of possible failures that the test technique can detect. Fault simulation: An empirical method used to determine how faults affect the operation of the circuit and also how much testing is required to obtain the desired fault coverage. IDD q testing: A parametric technique to monitor the current IDD that a circuit draws when it is in a quiescent state. It is used to detect faults which increase the normally low IDD . LFSR: A shift register formed by D flip-flops and EXOR gates, chained together, with a synchronous clock, used either as input pattern generator or as signature analyzer. MISR: Multiple-input LFSR. Off-line testing: Testing process carried out while the tested circuit is not in use. On-line testing: Concurrent testing to detect errors while circuit is in operation. Pseudo-random pattern generator: Generates a binary sequence of patterns where the bits appear to be random in the local sense (1 and 0 are equally likely), but they are repeatable (hence only pseudo-random). Random testing: The process of testing using a set of pseudo-randomly generated patterns. Sequential fault: A fault that causes a combinational circuit to behave like a sequential one. Signature analysis: A test where the responses of a device over time are compacted into a characteristic value called a signature, which is then compared to a known good one. Stuck-at fault: A fault model represented by a signal stuck at a fixed logic value (0 or 1). Test pattern (test vector): Input vector such that the faulty output is different from the fault-free output (the fault is stimulated and detected). Related Topic 23.2 Testing References M. Abramovici, M.A. Breuer and A.D. Friedman, Digital Systems Testing and Testable Design, Rockville, Md.: IEEE Press, 1992. P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques, New York: John Wiley and Sons, 1987. K. Cattell and J.C. Muzio, “Synthesis of one-dimensional linear hybrid cellular automata,” IEEE Trans. Computer Aided Design, vol. 15, no. 3, pp. 325–335, 1996. N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1993. T.W. Williams (Ed.), VLSI Testing, Amsterdam: North-Holland, 1986. Further Information The author would like to recommend reading the book by Abramovici et al. [1992] that, at the present time, gives the most comprehensive view of testing methods and design for testability. More information on deter￾ministic pattern generation can also be found in Fault Tolerant Computing, edited by D.K. Pradhan, and for