Laboratory Exercise 10 An Enhanced Processor In Laboratory Exercisewe described a simple processor.In Part I of that exercise the processor itself was in Pa are continued from those in Parts I and II in the preceding lab exercise. Part In this part you will extend the capability of the processor so that the external counter is no longer needed and sothat the procesr has the ability to perform read and write operations using memory or ther devices.You The ld (load)instruction loads noer)lowaoperation to be executed ony under a certain condition the condtio is that thecurre contents of register Gare not equal to0. Operation Function performed Id Rr.[Ryl Rz←【R st Rr.Ryl [B-[R mvnz Rz,Ry if GI=0,Rx-[Ry] Table 3.New instructions performed in the processor. A schematic of the enhanced processor is given in Figure 7.In this figure,registers RO to R6 are the same as in Figure I of Laboratory Exercise 9,but register R7 has been changed to a counter.This counter is used to provide the addresses in the memory fom which the procs sor's inst in the preceding lab the processor is reset,PCis set to address At the start of each instruction (in time step)the contents of PC opoint to the nex The processor's control unit increments PCby using thenrPCsignal,which is just an enable on this counter It is also possible to directly load an address into PC(R7)by having the processor execute a mvor mvi instruction contents of PCcan be copied into another register by using a m instruction.An example of code that uses the toa loopshwhere the text after the is just a comment.The plac es into R on sub This used ina larger program as a way of creating a delay. mvi mvi binary delay valu R5.R7 b R4.R2 mvnz R7R5 %continue subtracting until delay count gets to Laboratory Exercise 10 An Enhanced Processor In Laboratory Exercise 9 we described a simple processor. In Part I of that exercise the processor itself was designed, and in Part II the processor was connected to an external counter and a memory unit. This exercise describes subsequent parts of the processor design. Note that the numbering of figures and tables in this exercise are continued from those in Parts I and II in the preceding lab exercise. Part III In this part you will extend the capability of the processor so that the external counter is no longer needed, and so that the processor has the ability to perform read and write operations using memory or other devices. You will add three new types of instructions to the processor, as displayed in Table 3. The ld (load) instruction loads data into register RX from the external memory address specified in register RY. The st (store) instruction stores the data contained in register RX into the memory address found in RY. Finally, the instruction mvnz (move if not zero) allows a mv operation to be executed only under a certain condition; the condition is that the current contents of register G are not equal to 0. Operation Function performed ld Rx,[Ry] Rx ← [[Ry]] st Rx,[Ry] [Ry] ← [Rx] mvnz Rx, Ry if G != 0, Rx ← [Ry] Table 3. New instructions performed in the processor. A schematic of the enhanced processor is given in Figure 7. In this figure, registers R0 to R6 are the same as in Figure 1 of Laboratory Exercise 9, but register R7 has been changed to a counter. This counter is used to provide the addresses in the memory from which the processor’s instructions are read; in the preceding lab exercise, a counter external to the processor was used for this purpose. We will refer to R7 as the processor’s program counter (PC), because this terminology is common for real processors available in the industry. When the processor is reset, PC is set to address 0. At the start of each instruction (in time step 0) the contents of PC are used as an address to read an instruction from the memory. The instruction is stored in IR and the PC is automatically incremented to point to the next instruction (in the case of mvi the PC provides the address of the immediate data and is then incremented again). The processor’s control unit increments PC by using the incr_PC signal, which is just an enable on this counter. It is also possible to directly load an address into PC (R7) by having the processor execute a mv or mvi instruction in which the destination register is specified as R7. In this case the control unit uses the signal R7 in to perform a parallel load of the counter. In this way, the processor can execute instructions at any address in memory, as opposed to only being able to execute instructions that are stored in successive addresses. Similarly, the current contents of PC can be copied into another register by using a mv instruction. An example of code that uses the PC register to implement a loop is shown below, where the text after the % on each line is just a comment. The instruction mv R5,R7 places into R5 the address in memory of the instruction sub R4,R2. Then, the instruction mvnz R7,R5 causes the sub instruction to be executed repeatedly until R4 becomes 0. This type of loop could be used in a larger program as a way of creating a delay. mvi R2,#1 mvi R4,#10000000 % binary delay value mv R5,R7 % save address of next instruction sub R4,R2 % decrement delay count mvnz R7,R5 % continue subtracting until delay count gets to 0 1