kanda kiny entity butnot is u1 u2 port(x, y: in bit; z: out bit); end butnot architecture str of butnot is signal temp bit; component kin port (a: in bit; y: out bit) end component; component kand2 port(a, b: in bit; y: out bit);end componentVHDL中的结构设计的实例 entity butnot is port (x,y: in bit; z: out bit); end butnot; architecture str of butnot is signal temp: bit; component kinv port (a: in bit; y: out bit); end component; component kand2 port (a,b: in bit; y: out bit);end component;