Study the State Machine Design a How many State of this State Machine Idle State0. State01. State011. State0110. state01101 State011011 7 states, can use 3 bits to implement it a How many output from this design Match, State Machine(3 bits) 4 bit to implement it a How many Input signal for this design Serial in, State Machine (3 bits) 4 bits can implement it a Where is the Clock signal use for Use for the dff of the state machine Copyright 1997 Altera Corporation 2/22/2021P favaraCopyright © 1997 Altera Corporation 2/22/2021 P.6 Study the State Machine Design ◼ How many State of this State Machine – Idle, State0, State01, State011, State0110, State01101, State011011 • 7 states, can use 3 bits to implement it ◼ How many output from this design – Match, State_Machine (3 bits) • 4 bit to implement it ◼ How many Input signal for this design – Serial_in, State_Machine (3 bits) • 4 bits can implement it ◼ Where is the Clock signal use for – Use for the DFF of the State Machine