Representations of 1-order DSP System Basic elements y(n) x(n) x[n] y[n] 1/z 1/z Adder w[n] Block Diagram y[n] Multiplier xn&一→yn x(n) w[n] (n) 1 1/z Unit delayer x[n] D +y[n] Pick-off node x[n] →xn Signal Flow Diagram x[n] 2021/1/13 ASIC Design,by Yan Bo 132021/1/13 ASIC Design, by Yan Bo Representations of 1-order DSP System + 1/z 1/z x(n) 0 a 1 − b y(n) Block Diagram 1 a x(n) y(n) 1/z 1/z 0 a 1 a 1 − b Signal Flow Diagram Basic elements Adder Unit delayer A x[n] y[n] x[n] x[n] x[n] Multiplier Pick-off node x[n] y[n] w[n] + x[n]  y[n] w[n] −1 z x[n] y[n] 13 D