Table of Contents 1394 Open Host Controller Interface Specification Release 1.1 Printed 1/10/00 7.8.1.3 Block transmit....... 87 7.8.1.4 PHY packet transmit. 7.8.2 Asynchronous Transmit Responses.... 89 89 7.8.2.1 No-data transmit. 89 7.8.2.2 Quadlet transmit. 90 7.8.2.3 Block transmit... .91 7.8.3 Asynchronous Transmit Streams 93 8.Asynchronous Receive DMA.................. 95 8.1 AR DMA Context Programs............ 095 8.1.1 INPUT_MORE descriptor........... 95 8.1.2 AR DMA descriptor usage............. .96 8.2 bufferFill mode........ .97 8.3 Asynchronous Receive Context Registers.............. 97 8.3.1AR DMA Commandptr register9 8.3.2 AR ContextControl register(set and clear)... .98 8.4 AR DMA Controller.. .98 8.4.1 Asynchronous Filter Registers... 98 8.4.2 AR DMA Controller processing. .99 8.4.2.1 AR DMA Packet Trailer ,100 8.4.2.2 Error Handling......... .100 8.4.2.3 Bus Reset Packet...... 101 8.5 PHY Packets.… …102 8.6 Asynchronous Receive Interrupts...... .102 8.7 Asynchronous Receive Data Formats........ .103 8.7.1 Asynchronous Receive Requests............... .104 8.7.1.1 No-data receive......... .104 8.7.1.2 Quadlet Receive......... ,104 8.7.1.3 Block receive..... ,106 8.7.1.4 PHY packet receive.... 107 8.7.2 Asynchronous Receive Responses 108 8.7.2.1 No-data receive..... .108 8.7.2.2 Quadlet Receive ,108 8.7.2.3 Block receive........... .109 9.Isochronous Transmit DMA........ .111 9.1 IT DMA Context Programs.......... .111 9.1.1 IT DMA command descriptor overview.... .111 9.1.2 OUTPUT MORE descriptor... .112 9.1.3 OUTPUT MORE-Immediate descriptor. .113 9.1.4 OUTPUT LAST descriptor................. 114 9.1.5 OUTPUT LAST-Immediate descriptor... .115 9.1.6 STORE VALUE descriptor.. .116 9.1.7 IT DMA descriptor usage.......... ..117 9.2 IT Context Registers. .118 9.2.1C0 mmandPtr............. ...118 9.2.2 IT ContextControl Register.... ,119 9.3 Isochronous transmit DMA controller..... ..120 9.3.1 IT DMA Processing............ ,121 9.3.2 Prefetching IT Packets.... .122 9.3.3 Isochronous Transmit Cycle Loss .122 9.3.4 Skip Processing Overflow 123 Page viii Copyright 1996-2000 All rights reserved.Page viii Copyright © 1996-2000 All rights reserved. Table of Contents 1394 Open Host Controller Interface Specification / Release 1.1 Printed 1/10/00 7.8.1.3 Block transmit ...............................................................................................................................87 7.8.1.4 PHY packet transmit .....................................................................................................................89 7.8.2 Asynchronous Transmit Responses..........................................................................................................89 7.8.2.1 No-data transmit............................................................................................................................89 7.8.2.2 Quadlet transmit ............................................................................................................................90 7.8.2.3 Block transmit ...............................................................................................................................91 7.8.3 Asynchronous Transmit Streams..............................................................................................................93 8. Asynchronous Receive DMA ...........................................................................................................................................95 8.1 AR DMA Context Programs...............................................................................................................................95 8.1.1 INPUT_MORE descriptor........................................................................................................................95 8.1.2 AR DMA descriptor usage.......................................................................................................................96 8.2 bufferFill mode ...................................................................................................................................................97 8.3 Asynchronous Receive Context Registers...........................................................................................................97 8.3.1 AR DMA CommandPtr register...............................................................................................................97 8.3.2 AR ContextControl register (set and clear) ..............................................................................................98 8.4 AR DMA Controller ...........................................................................................................................................98 8.4.1 Asynchronous Filter Registers .................................................................................................................98 8.4.2 AR DMA Controller processing ..............................................................................................................99 8.4.2.1 AR DMA Packet Trailer ..............................................................................................................100 8.4.2.2 Error Handling ............................................................................................................................100 8.4.2.3 Bus Reset Packet .........................................................................................................................101 8.5 PHY Packets .....................................................................................................................................................102 8.6 Asynchronous Receive Interrupts .....................................................................................................................102 8.7 Asynchronous Receive Data Formats ...............................................................................................................103 8.7.1 Asynchronous Receive Requests............................................................................................................104 8.7.1.1 No-data receive............................................................................................................................104 8.7.1.2 Quadlet Receive ..........................................................................................................................104 8.7.1.3 Block receive...............................................................................................................................106 8.7.1.4 PHY packet receive .....................................................................................................................107 8.7.2 Asynchronous Receive Responses .........................................................................................................108 8.7.2.1 No-data receive............................................................................................................................108 8.7.2.2 Quadlet Receive ..........................................................................................................................108 8.7.2.3 Block receive...............................................................................................................................109 9. Isochronous Transmit DMA...........................................................................................................................................111 9.1 IT DMA Context Programs ..............................................................................................................................111 9.1.1 IT DMA command descriptor overview.................................................................................................111 9.1.2 OUTPUT_MORE descriptor..................................................................................................................112 9.1.3 OUTPUT_MORE-Immediate descriptor................................................................................................113 9.1.4 OUTPUT_LAST descriptor ...................................................................................................................114 9.1.5 OUTPUT_LAST-Immediate descriptor .................................................................................................115 9.1.6 STORE_VALUE descriptor ...................................................................................................................116 9.1.7 IT DMA descriptor usage.......................................................................................................................117 9.2 IT Context Registers .........................................................................................................................................118 9.2.1 CommandPtr ..........................................................................................................................................118 9.2.2 IT ContextControl Register....................................................................................................................119 9.3 Isochronous transmit DMA controller ..............................................................................................................120 9.3.1 IT DMA Processing ...............................................................................................................................121 9.3.2 Prefetching IT Packets ...........................................................................................................................122 9.3.3 Isochronous Transmit Cycle Loss ..........................................................................................................122 9.3.4 Skip Processing Overflow......................................................................................................................123