■ create your VHDL file Fe Untitled2- Text Editor entity test is port ( a: in std logic; b:out std logic); architecutre a of test is begin b < not a. end a? Copyright 1997 Altera Corporation 2/22/2021P favaraCopyright © 1997 Altera Corporation 2/22/2021 P.6 ◼ create your VHDL file