Contents RM0394 6.2.10 Clock security system(CSS) 6.2.11 Clock security system on LSE...............................187 6212 ADC clock ,187 62.13 RTCclock 187 6.2.14 ,188 6.2.15 Watchdog clock 188 6.2.16 Clock-out capability 6.2.17 Intemnal/extemal clock measurement with TIM15IM16 ..189 6218 191 6.3 Low-power modes 191 6.4 RCC registers 193 6.4.1 Clock control register (RCC CR)........... ,193 6.4.2 Intemal clock sources calibration register(RCC_ICSCR) 196 6.43 Clock configuration register (RCC_CFGR) 6.4.4 PLL configuration register (RCC PLLCFGR) 198 PLLSAI1 configuration register(RCC_PLLSAI1CFGR) 201 Clock interrupt enable register(RCC_CIER) 。。。 204 6.4.7 Clock interrupt flag register(RCC CIFR) 206 648 Clock interrupt clear register(RCC_CICR 207 6.4.9 AHB1 peripheral reset register(RCC_AHB1RSTR) 208 6.4.10 AHB2 peripheral reset register(RCC_AHB2RSTR) 209 6.4.11 AHB3 peripheral reset register(RCC_AHB3RSTR) 211 6.4.12 APB1 peripheral reset register 1(RCC APB1RSTR1) 211 64.13 APB1 peripheral reset register 2(RCC_APB1RSTR2) 214 6.4.14 APB2 peripheral reset register(RCC_APB2RSTR) 215 6.415 AHB1 peripheral clock enable register(RCC AHB1ENR) 216 6.4.16 AHB2 peripheral clock enable register(RCC_AHB2ENR) 218 6.4.17 AHB3 peripheral clock enable register(RCC AHB3ENR)...... 219 6.4.18 APB1 peripheral clock enable register 1(RCC_APB1ENR1) 6.4.19 APB1 peripheral clock enable register 2(RCC_APB1ENR2) 6.4.20 APB2 peripheral clock enable register(RCC_APB2ENR). .224 6.4.21 ocks enable in Sleep and Stop modes register 225 6.422 enable in Sleep and Stop modes registe AHB2SMENR) 226 6.4.23 cks AHB3SMENR enable in Sleep and Stop modes registe .228 6/1600 RM0394 Rev 4 7Contents RM0394 6/1600 RM0394 Rev 4 6.2.10 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.2.11 Clock security system on LSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.12 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.13 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 6.2.14 Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.2.15 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.2.16 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 6.2.17 Internal/external clock measurement with TIM15/TIM16 . . . . . . . . . . . 189 6.2.18 Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy) . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 6.4 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.4.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 6.4.2 Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 196 6.4.3 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 196 6.4.4 PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . . . . . 198 6.4.5 PLLSAI1 configuration register (RCC_PLLSAI1CFGR) . . . . . . . . . . . 201 6.4.6 Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 204 6.4.7 Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 206 6.4.8 Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 207 6.4.9 AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . . . . . 208 6.4.10 AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . . . . . 209 6.4.11 AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . . . . . 211 6.4.12 APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . . . . . 211 6.4.13 APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . . . . . 214 6.4.14 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 215 6.4.15 AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . . . . . 216 6.4.16 AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . . . . . 218 6.4.17 AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . . . . . . . 219 6.4.18 APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . . . . 220 6.4.19 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . . . . 222 6.4.20 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 224 6.4.21 AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.4.22 AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 6.4.23 AHB3 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228