s5165a580741E6 OCTOBER 1976-REVISED MARCH 1988 Complementary Outputs JOR W PACKAGE Direct Overriding Load(Data)Inputs Gated Clock Inputs (TOP VIEW) Parallel-to-Serial Data Conversion CL 20 description PAC clocked. Par ea Th de-clamped to minimize transmission-line effects, 3272019 eby simplifying system desigr Clockingisaccomplished througha 2-input positive outs high bits clocking and holding eithe nput 三 kinhibit input should be d to the high vel only while the Paral 话兰舌 outs are loade directh into the registe ogic symbolt of the SH/LD1 UNCTION TABLE CLK INH 2 C2/ CLK SER 121 H 3 4 5 91 H 6) 1D 1984 and EC e for D.J.N.and W package 2-521 POST OFFICE BOX 655012 DALLAS.TEXAS 75265