① IEEE 754 FLOATING-POINT ▣ OPCODES.BASE CONVERSION.ASCII SYMBOLS STANDARD IEEE 754 Symbols MIPS (1)MIPS (2)MIPS opeode Deci.Hexa.ASCII Deei.Hexa.ASCIT funct futct Binary dec.Char. dech Char 0 生0 (3126 (5:0) (50 mal mal (-1)x(1+Fraction)x 2(Exponent-Bias) 0 acter 士Denorm a11 a8d. 00000D0 0 O NUL 64 40 where Single Precision Bias-127. 0 00000D1 SOH 65 41 Double Precision Bias-1023. T to MAX-I anything F.Pt.Num. arl 000010 66 MAX 0 生o 1a1 ata 000011 3 3 上 A3 IEEE Single Precision and MAX 主0 NaN pue sllv Ud】[U 上 08 5 9 Double Precision Formats: S.P.MAX -255.D.P.MAX -2047 abs./ 000I01 ENO 000110 ACK 7 S Exponent Fraction bgt需 srav 000111 67 BEL 71 47 3130 232 0o00U B HT 7 s Exponent Fraction 74 632 a1七1 5251 OVZ a1r九rn 0010I1 b VT 75 4b MEMORY ALLOCATION STACK FRAME andi Found.w./)1100 Stack Higher 0￥1 00110 CR 77 d Argument 6 Memory 见后三1 c811.f 001110 14 78 Argument S Addresses 1u1 r1oor.w/001111 15 79 r DLE (2) 勇h 010001 I 81 aved Registers Stack novz. Dynamic Data 0I0o10 18 12 DC2 82 Grows movn./ 010011 9 Sgp+10008s000ea 1 DC3 Statie Data 10000000h ocal Variables 010101 21 15 NAK 010110 22 SYN Text 010111 pe00400000hex Lower u1七 U00 2 18 CAN 38 Memory Addresses 周B1七u 011001 )气 19 EM 59 Reserved div 011010 26 SUB 90 divu 011011 91 DATA ALIGNMENT O1100 28 FS 92 93 Double Word I 3 e 94 Word Word 011111 31 US 95 1 Halfword Halfword Halfword Halfword 1b cvt.a了 ④ addu cvt.df 10000 33 21 ByteByte Byte Byte Byte Byte Byte Byte 1w1 线o 1000I0 10011 35 9 63 Value of three least significant bits of byte address(Big Endian) cvt.w./ 00I00 0而 EXCEPTION CONTROL REGISTERS:CAUSE AND STATUS ox 100I01 101 B Interrupt Exception 10D110 诏 & 102 6 100111 103 6 D Mask Code 5101e b 31 sh 101001 41 29 105 69 Pending U EI sIt 101010 106 6 sItu 101011 Interrupt 3 M LE I= 108 BD-Branch Delay,UM-User Mode.EL-Exception Level,IE -Interrupt Enable 101101 45 109 6d EXCEPTION CODES WE 101110 46 2e 110 111 f Number Name Number Name 101111 Cause of Exception Cause of Exception 11 ctr 1000 48 30 0 112 70 0 Int Bp Breakpoint Exception c.un/ 9 31 113 Aderess frror exception AdEL 10 RI Reserved Instruction c.g./ 110010 14 (load or instruction fetch) Exception pror tItu c.ueg 110011 51 115 73 5 AdEs Address上rot上Excep0n 116 11 CpU Coprocessor c.olt. (store) mplemented 41 c.ult. 110101 53 5 17 15 IBE Bus Error on 12 Ov 1g2 tne 0.010 110110 6 118 6 6 Instruction Fetch Exception c.ulaf 110111 车写 119 7 c.st 36 DBE Bus Error on 13 Tr Load or Store Trap swcl 111001 9 121 8 58 Sys Syscall Exception 15 FPE Floating Point Exception 111010 3a 122 7a c.ngi/ 111011 123 SIZE PREFIXES (10%for Disk,Communication:2*for Memory) 125 7d PRE. PRE. PRE. PRE. 111101 61 SIE 7 c.1/ 111110 62 3 126 FIX FIX SIZE FIX FIX c.ng 111111 6 27 DEL 103,20Klo 105,20Peta- 10 milli- femto- (1)opcode(31F26)=0 10,220Mega 101,2Exa 106 micro- 10客 (2)opcode(31:26)--17n (1lhex):if fmt(25:21) 16in (10pex)s (single): 10.20Gga 1021,270 Zetta. 109a0- 1027 if fmnt(25:21)-17n()f-d (double) 102 240 Tera- 10,20Yota 0 yocto- The symbol for each prefix is just its first letter,except u is used for micro. Copyright 2009 by Elsevier,Ine.,All rights reserved.From Patterson and Hennessy.Computer Organization and Design,4th ed. SaIW... Argument 6 Argument 5 Saved Registers Local Variables OPCODES, BASE CONVERSION, ASCII SYMBOLS (1) opcode(31:26) == 0 (2) opcode(31:26) == 17ten (11hex); if fmt(25:21)==16ten (10hex) f = s (single); if fmt(25:21)==17ten (11hex) f = d (double) STANDARD (-1)S × (1 + Fraction) × 2(Exponent - Bias) where Single Precision Bias = 127, Double Precision Bias = 1023. IEEE Single Precision and Double Precision Formats: MEMORY ALLOCATION $sp 7fff fffchex $gp 1000 8000hex 1000 0000hex pc 0040 0000hex 0hex DATA ALIGNMENT EXCEPTION CONTROL REGISTERS: CAUSE AND STATUS EXCEPTION CODES SIZE PREFIXES (10x for Disk, Communication; 2x for Memory) The symbol for each prefix is just its first letter, except μ is used for micro. MIPS opcode (31:26) (1) MIPS funct (5:0) (2) MIPS funct (5:0) Binary Deci￾mal Hexa￾deci￾mal ASCII Char￾acter Deci￾mal Hexa￾deci￾mal ASCII Char￾acter (1) sll add.f 00 0000 0 0 NUL 64 40 @ sub.f 00 0001 1 1 SOH 65 41 A j srl mul.f 00 0010 2 2 STX 66 42 B jal sra div.f 00 0011 3 3 ETX 67 43 C beq sllv sqrt.f 00 0100 4 4 EOT 68 44 D bne abs.f 00 0101 5 5 ENQ 69 45 E blez srlv mov.f 00 0110 6 6 ACK 70 46 F bgtz srav neg.f 00 0111 7 7 BEL 71 47 G addi jr 00 1000 8 8 BS 72 48 H addiu jalr 00 1001 9 9 HT 73 49 I slti movz 00 1010 10 a LF 74 4a J sltiu movn 00 1011 11 b VT 75 4b K andi syscall round.w.f 00 1100 12 c FF 76 4c L ori break trunc.w.f 00 1101 13 d CR 77 4d M xori ceil.w.f 00 1110 14 e SO 78 4e N lui sync floor.w.f 00 1111 15 f SI 79 4f O mfhi 01 0000 16 10 DLE 80 50 P (2) mthi 01 0001 17 11 DC1 81 51 Q mflo movz.f 01 0010 18 12 DC2 82 52 R mtlo movn.f 01 0011 19 13 DC3 83 53 S 01 0100 20 14 DC4 84 54 T 01 0101 21 15 NAK 85 55 U 01 0110 22 16 SYN 86 56 V 01 0111 23 17 ETB 87 57 W mult 01 1000 24 18 CAN 88 58 X multu 01 1001 25 19 EM 89 59 Y div 01 1010 26 1a SUB 90 5a Z divu 01 1011 27 1b ESC 91 5b [ 01 1100 28 1c FS 92 5c \ 01 1101 29 1d GS 93 5d ] 01 1110 30 1e RS 94 5e ^ 01 1111 31 1f US 95 5f _ lb add cvt.s.f 10 0000 32 20 Space 96 60 ‘ lh addu cvt.d.f 10 0001 33 21 ! 97 61 a lwl sub 10 0010 34 22 " 98 62 b lw subu 10 0011 35 23 # 99 63 c lbu and cvt.w.f 10 0100 36 24 $ 100 64 d lhu or 10 0101 37 25 % 101 65 e lwr xor 10 0110 38 26 & 102 66 f nor 10 0111 39 27 ’ 103 67 g sb 10 1000 40 28 ( 104 68 h sh 10 1001 41 29 ) 105 69 i swl slt 10 1010 42 2a * 106 6a j sw sltu 10 1011 43 2b + 107 6b k 10 1100 44 2c , 108 6c l 10 1101 45 2d - 109 6d m swr 10 1110 46 2e . 110 6e n cache 10 1111 47 2f / 111 6f o ll tge c.f.f 11 0000 48 30 0 112 70 p lwc1 tgeu c.un.f 11 0001 49 31 1 113 71 q lwc2 tlt c.eq.f 11 0010 50 32 2 114 72 r pref tltu c.ueq.f 11 0011 51 33 3 115 73 s teq c.olt.f 11 0100 52 34 4 116 74 t ldc1 c.ult.f 11 0101 53 35 5 117 75 u ldc2 tne c.ole.f 11 0110 54 36 6 118 76 v c.ule.f 11 0111 55 37 7 119 77 w sc c.sf.f 11 1000 56 38 8 120 78 x swc1 c.ngle.f 11 1001 57 39 9 121 79 y swc2 c.seq.f 11 1010 58 3a : 122 7a z c.ngl.f 11 1011 59 3b ; 123 7b { c.lt.f 11 1100 60 3c < 124 7c | sdc1 c.nge.f 11 1101 61 3d = 125 7d } sdc2 c.le.f 11 1110 62 3e > 126 7e ~ c.ngt.f 11 1111 63 3f ? 127 7f DEL S Exponent Fraction 31 30 23 22 0 S Exponent Fraction 63 62 52 51 0 Double Word Word Word Byte Byte Byte Byte Byte Byte Byte Byte 0 1 2 3 4 5 6 7 Value of three least significant bits of byte address (Big Endian) B D Interrupt Mask Exception Code 31 15 8 6 2 Pending Interrupt U M E L I E 15 8 4 1 0 Number Name Cause of Exception Number Name Cause of Exception 0 Int Interrupt (hardware) 9 Bp Breakpoint Exception 4 AdEL Address Error Exception (load or instruction fetch) 10 RI Reserved Instruction Exception 5 AdES Address Error Exception (store) 11 CpU Coprocessor Unimplemented 6 IBE Bus Error on Instruction Fetch 12 Ov Arithmetic Overflow Exception 7 DBE Bus Error on Load or Store 13 Tr Trap 8 Sys Syscall Exception 15 FPE Floating Point Exception SIZE PRE￾FIX SIZE PRE￾FIX SIZE PRE￾FIX SIZE PRE￾FIX 103, 210 Kilo- 1015, 250 Peta- 10-3 milli- 10-15 femto- 106, 220 Mega- 1018, 260 Exa- 10-6 micro- 10-18 atto- 109, 230 Giga- 1021, 270 Zetta- 10-9 nano- 10-21 zepto- 1012, 240 Tera- 1024, 280 Yotta- 10-12 pico- 10-24 yocto- 3 Stack Dynamic Data Static Data Text Reserved IEEE 754 Symbols S.P. MAX = 255, D.P. MAX = 2047 Exponent Fraction Object 0 0 ± 0 0 ≠0 ± Denorm 1 to MAX - 1 anything ± Fl. Pt. Num. MAX 0 ±∞ MAX ≠0 NaN STACK FRAME Higher Memory Addresses Lower Memory Addresses Stack Grows $sp $fp 4 MIPS Reference Data Card (“Green Card”) 1. Pull along perforation to separate card 2. Fold bottom side (columns 3 and 4) together IEEE 754 FLOATING-POINT Halfword Halfword Halfword Halfword BD = Branch Delay, UM = User Mode, EL = Exception Level, IE =Interrupt Enable Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design, 4th ed