For many of the signals in a design, the bad properties of the wires are irrelevant, for the same reason that we can afford to ignore combinational logic hazards-we don t look at the wires until they behave well. This works fine except for the wires used for timing signals in our design. Here are some general guidelines if you want to be careful 1. Keep wires short. The shorter your wires are, the less chance of noise pickup, coupling, and other undesirable behavior 2. Drive a wire from one end or the other of the string of places it goes, not from the midd 3. Wire all the places a signal goes sequentially, one after another, not as some sort of tree-structure. This applies to single electrical runs 4. If you have trouble with making your signals look good on a run, consider resistor termination of the far end of the run. Your friend here is your oscilloscope. Does the signal look like it has clean edges in the positive and negative going directions? Is there ringing or strong over and undershoot? Your termination will have to be a Thevenin equivalent resistor to about +3 volts with an impedance of about 150 ohms(bet you thought you would never hear about those again, didn 't you.) 5. Undershoot on LS series logic, particularly, can lead to drastic changes in the guaranteed Tplh and Tphl speeds for parts. If you can't understand why the part which says it should be a 10ns part takes 20ns to switch, check for the 1.5 volt undershoot on its input. Remember that the spec sheet is your contract with the part manufacturer. He doesn,'t guarantee the behavior if you are feeding garbage into the part 6. Bundling wires together makes your kit look neat, but it also makes a good transformer. Unfortunately, you probably didn,'t want a transformer between you logic signals. For clock signals, route the critical wires far away from other wires particularly wide parallel busses switching at the same time. You might consider twisted pair, which wraps a ground wire around the signal wire. Ground both ends of the twisted pair ground Clock distribution Clocks, and write pulses for RAMs are the most sensitive logic signals in a typical design. The design methodology which we are teaching in this course allows most signal in a machine to have hazards, ringing, and even be slow, without actually making the circuit you are designing not work. The penalty for sloppiness in most signals is simply that the circuit will operate slower, rather than not at all This is not the case with clock signals. If a clock has ringing on it, or a slow rise time then your circuit may not work AT ALL. It pays then to take special distributing the clock. Loading rules should be strictly obeyed(they should be anyway, of course) A more insidious problem sometimes occurs, however, due to the possibility of CLOCK SKEW. This means when the clocks for different portions of your logic design have their rising edges occur at slightly different times. This can happen as a result of long wires inFor many of the signals in a design, the bad properties of the wires are irrelevant, for the same reason that we can afford to ignore combinational logic hazards-we don't look at the wires until they behave well. This works fine except for the wires used for timing signals in our design. Here are some general guidelines if you want to be careful: 1. Keep wires short. The shorter your wires are, the less chance of noise pickup, coupling, and other undesirable behavior. 2. Drive a wire from one end or the other of the string of places it goes, not from the middle. 3. Wire all the places a signal goes sequentially, one after another, not as some sort of tree-structure. This applies to single electrical runs. 4. If you have trouble with making your signals look good on a run, consider resistor termination of the far end of the run. Your friend here is your oscilloscope. Does the signal look like it has clean edges in the positive and negative going directions? Is there ringing or strong over and undershoot? Your termination will have to be a Thevenin equivalent resistor to about +3 volts with an impedance of about 150 ohms (bet you thought you would never hear about those again, didn't you ...). 5. Undershoot on LS series logic, particularly, can lead to drastic changes in the guaranteed Tplh and Tphl speeds for parts. If you can't understand why the part which says it should be a 10ns part takes 20ns to switch, check for the 1.5 volt undershoot on its input. Remember that the spec sheet is your contract with the part manufacturer. He doesn't guarantee the behavior if you are feeding garbage into the part. 6. Bundling wires together makes your kit look neat, but it also makes a good transformer. Unfortunately, you probably didn't want a transformer between you logic signals. For clock signals, route the critical wires far away from other wires, particularly wide parallel busses switching at the same time. You might consider twisted pair, which wraps a ground wire around the signal wire. Ground both ends of the twisted pair ground. Clock Distribution Clocks, and write pulses for RAM's are the most sensitive logic signals in a typical design. The design methodology which we are teaching in this course allows most signals in a machine to have hazards, ringing, and even be slow, without actually making the circuit you are designing not work. The penalty for sloppiness in most signals is simply that the circuit will operate slower, rather than not at all. This is not the case with clock signals. If a clock has ringing on it, or a slow rise time, then your circuit may not work AT ALL. It pays then to take special care in distributing the clock. Loading rules should be strictly obeyed (they should be anyway, of course). A more insidious problem sometimes occurs, however, due to the possibility of CLOCK SKEW. This means when the clocks for different portions of your logic design have their rising edges occur at slightly different times. This can happen as a result of long wires in