the clock circuit, from different numbers of gates in series with different clocks in the machine, from different loading on different clocks, and from lots of other reasons Whatever the reasons, clock skew is a common source of problems. To see why, consider a pair of type D flip-flop registers, such as LS374 parts, each clocked by a different clock. It may be your intention to load data first into register 1 on the first clock, and then into register 2 from the outputs of register 1 on a second clock. If the clock on register the part, then the incorrect data will be loaded into register 2: namely, register z wof lags the clock on register 2 by more than the sum of the setup and propagation delays of receive the data NEWlY clocked into register 1. So it is important to keep the location of the clock edge synchronized over the entire diagram. This is hard sometimes drives a set of four gates, each of whose outputs fans out to four more gates, whose 16 One technique to use is to build a"tree"of clock distribution The main clock generato outputs each drive a section of the machine's clock. Try to keep wire lengths the same and to keep the clock runs as short as possible. Loads should be distributed evenly across all of the clocks available. With the logic family you are using in the course, clock skew should not be a major problem. You should be aware of its existence, though Gating the clock Don,'t do it. This is one of the most common problems novice digital designers encounter Assume you are using positive edge triggered logic. Your clock can be thought of then a" low asserted"signal. If you were to gate if off, you would use a positive Or gate hold it high. Unfortunately, you need to start holding it high BEFORE it goes LoW Gating it off after the clock goes low will actually just make a positive transition of the clock occur slightly early Clock skews can also arise from being careless in gating clocks. If you absolutely can 't contain yourself, and must gate a clock, use a clock from before the final clock fanout to compensate for the gate delay in the gating circuit Gating of a clock can almost always be avoided by using registers with a clock enable input. Counter and shift register parts can also be forced into the do nothing"state easily RAM Write pulses Write pulses for static memories are likely to be one of the few areas where you do need to gate a clock-like waveform with a logic signal. Since the RaM parts available act as latches, it is important that the signals used to gate the write enable off, and that the address input and clock enable signals arrive early enough during the clock enable cycle not to cause glitches in the RAM functioning. To help you meet the Thold requirement of some parts, it is often helpful if your timing generator terminates the write pulse slightly prior to the rising edge of the main clock, assur Thold. You can ofte make the clock signal of a design have a short enough Tlow such that it can be used asthe clock circuit, from different numbers of gates in series with different clocks in the machine, from different loading on different clocks, and from lots of other reasons. Whatever the reasons, clock skew is a common source of problems. To see why, consider a pair of type D flip-flop registers, such as LS374 parts, each clocked by a different clock. It may be your intention to load data first into register 1 on the first clock, and then into register 2 from the outputs of register 1 on a second clock. If the clock on register 1 lags the clock on register 2 by more than the sum of the setup and propagation delays of the part, then the incorrect data will be loaded into register 2: namely, register 2 will receive the data NEWLY clocked into register 1. So it is important to keep the location of the clock edge synchronized over the entire diagram. This is hard sometimes. One technique to use is to build a ``tree" of clock distribution: The main clock generator drives a set of four gates, each of whose outputs fans out to four more gates, whose 16 outputs each drive a section of the machine's clock. Try to keep wire lengths the same and to keep the clock runs as short as possible. Loads should be distributed evenly across all of the clocks available. With the logic family you are using in the course, clock skew should not be a major problem. You should be aware of its existence, though. Gating the Clock Don't do it. This is one of the most common problems novice digital designers encounter. Assume you are using positive edge triggered logic. Your clock can be thought of then as a ``low asserted" signal. If you were to gate if off, you would use a positive OR gate to hold it high. Unfortunately, you need to start holding it high BEFORE it goes LOW. Gating it off after the clock goes low will actually just make a positive transition of the clock occur slightly early. Clock skews can also arise from being careless in gating clocks. If you absolutely can't contain yourself, and must gate a clock, use a clock from before the final clock fanout to compensate for the gate delay in the gating circuit. Gating of a clock can almost always be avoided by using registers with a clock enable input. Counter and shift register parts can also be forced into the ``do nothing" state easily. RAM Write Pulses Write pulses for static memories are likely to be one of the few areas where you do need to gate a clock-like waveform with a logic signal. Since the RAM parts available act as latches, it is important that the signals used to gate the write enable off, and that the address input and clock enable signals arrive early enough during the clock enable cycle not to cause glitches in the RAM functioning. To help you meet the Thold requirement of some parts, it is often helpful if your timing generator terminates the write pulse slightly prior to the rising edge of the main clock, assuring an adequate Thold. You can often make the clock signal of a design have a short enough Tlow such that it can be used as