nd kreg16 architecture beh of kregl6 is signal ig: std logic vector(I to 16); if clr='I'then iq<=(others=>0) elsif clk'event and clk=1' then coke I' then 1q <=d: end if if oe=I'then q<=iq: 多种功能的寄存器设计比较 use ieee std logic 1164. all; ntity regine port(d, clk, clr, pre,load, data: in bit q1, 2, 93, 94, q5, 96, q7: out bit); architecture beh of reginf is clk为1时寄存d wait until clk=1'ql<=d;,-利用ck上升沿传递信号 clk为0时寄存dend kreg16; architecture beh of kreg16 is signal iq: std_logic_vector(1 to 16); begin process ( clk,clr,oe,iq) begin if clr='1' then iq<=(others=>'0'); elsif clk'event and clk='1' then if clken = '1' then iq<=d; end if; end if ; if oe='1' then q <= iq; else q<=(others=>'Z'); end if; end process ; end beh; 多种功能的寄存器设计比较 library ieee; use ieee.std_logic_1164.all; entity reginf is port(d,clk,clr,pre,load,data: in bit; q1,q2,q3,q4,q5,q6,q7: out bit); end reginf; architecture beh of reginf is begin -- clk 为 1 时寄存 d process begin wait until clk='1'; q1<=d; --利用 clk 上升沿传递信号； end process; -- clk 为 0 时寄存 d process