下降沿D触发器描述 方法一:使用信号属性函数 LIBRARY IEEE USE IEEESTD LOGIC 1164.ALL; ENTITY D reg Is PORT,CP: IN STD LOGIC Q: OUTSTD LOGIC); END D reg; ARCHITECTURE test OF D reg Is BEGIN PROCESS(CP) BEGIN IF(CPEVENT AND CP=0)THEN <=D END PROCESS END test下降沿D触发器描述 方法一：使用信号属性函数 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS(CP) BEGIN IF (CP’EVENT AND CP=‘0’) THEN Q<=D; END PROCESS; END test;