38译码器74138:反函数输出采用选择代入语句实现 图5-3774x1383-8译码器 逻图(包括标准16脚双列直插式封装的引脚编号)(b)传统逻辑符号 library ieee use ieee std logic 1164.all entity v74x138 is port(gl, gal, g2bl: in std logic a: in std logic vector(2 downto O) yl: out std logic vector( 0 to 7)) end v74x138 architecture rtl of v74x138 is signal yli std logic vector(0 to 7); with a select yli<= o111lll1" when 000 "10111111 when "001 "11011111" when 010 11101111 when01l 11110111"when"100 "11111011"when "101" "11111101" when"110" "11111110"when "1ll" 11111111"when others3-8 译码器 74138 ：反函数输出 采用选择代入语句实现 library ieee; use ieee.std_logic_1164.all; entity v74x138 is port (g1,g2al,g2bl: in std_logic; a: in std_logic_vector(2 downto 0); yl: out std_logic_vector( 0 to 7)); end v74x138; architecture rtl of v74x138 is signal yli:std_logic_vector(0 to 7); begin with a select yli<= "01111111" when "000", "10111111" when "001", "11011111" when "010", "11101111" when "011", "11110111" when "100", "11111011" when "101", "11111101" when "110", "11111110" when "111", "11111111" when others;