0我15 SRAM D/a 15 以靠 a.71 鞋2睡 0.5 5 4 4 3 3 2 2 1 1 D D C C B B A A AUD_BCLK AUD_DACDAT AUD_DACLRCK LED[5..26] AUD_ADCLRCK I2C_SCLK AUD_XCK UART_TXD PS2_CLK LED[0..4] IRDA_TXD ENET_CMD ENET_IOR ENET_CS ENET_IOW ENET_INT ENET_D[0..15] 25MHZ ENET_RESET AUD_BCLK AUD_DACDAT AUD_ADCLRCK AUD_DACLRCK I2C_SCLK AUD_XCK AUD_ADCDAT I2C_SDAT HEX0_D[0..6] HEX1_D[0..6] HEX2_D[0..6] HEX3_D[0..6] HEX4_D[0..6] HEX5_D[0..6] HEX6_D[0..6] HEX7_D[0..6] LCD_D[0..7] LCD_BLON LCD_ON LCD_WR LCD_EN LCD_RS LED[0..26] PS2_DAT KEY[0..3] GPIO_B[0..71] SW[0..17] IRDA_TXD IRDA_RXD EXT_CLOCK 50MHZ PS2_CLK UART_TXD UART_RXD FLASH_A[0..21] DRAM_CLK DRAM_CKE DRAM_BA0 DRAM_BA1 SD_DAT DRAM_WE DRAM_CAS DRAM_RAS DRAM_CS SRAM_A[0..17] SD_DAT3 SD_CMD SD_CLK FLASH_CE FLASH_OE DRAM_D[0..15] DRAM_LDQM DRAM_UDQM NCSO ASDO DCLK TDI TMS TCK NCONFIG NCE CONF_DONE NSTATUS LINK_D0 LINK_D1 LINK_D2 OTG_INT1 OTG_INT0 OTG_DREQ1 OTG_DREQ0 OTG_WE OTG_OE OTG_RESET OTG_DACK0 OTG_DACK1 OTG_CS OTG_A1 OTG_A0 DATA0 TDO LINK_D3 12MHZ 12MHZ OTG_LSPEED OTG_FSPEED OTG_D[0..15] SRAM_D[0..15] DRAM_A[0..11] SRAM_WE SRAM_CE SRAM_OE SRAM_UB SRAM_LB FLASH_D[0..7] FLASH_RESET FLASH_WE TD_D[0..7] TD_HS 27MHz TD_VS TD_RESET I2C_SCLK I2C_SDAT VGA_BLANK VGA_SYNC VGA_CLOCK VGA_HS VGA_VS VGA_R[0..9] VGA_G[0..9] VGA_B[0..9] FLASH_D[0..7] 50MHZ UART_RXD PS2_DAT SW[0..2] EXT_CLOCK SW[3..5] SW[6..9] KEY[0..3] GPIO_B[0..71] SW[10..17] IRDA_RXD FLASH_CE FLASH_OE FLASH_RESET FLASH_WE FLASH_A[0..21] AUD_ADCDAT I2C_SDAT ENET_CMD ENET_RESET 25MHZ ENET_CS ENET_IOR ENET_IOW ENET_INT ENET_D[0..15] HEX6_D[0..6] HEX4_D[0..6] HEX5_D[0..6] HEX7_D[0..6] LCD_EN LCD_WR LCD_ON LCD_BLON LCD_RS LCD_D[0..7] HEX3_D[0..6] HEX2_D[0..6] HEX1_D[0..6] HEX0_D[0..6] SRAM_CE SRAM_WE SRAM_OE SRAM_UB SRAM_LB SRAM_A[0..17] DRAM_CS DRAM_BA1 DRAM_CAS DRAM_CLK DRAM_A[0..11] DRAM_LDQM DRAM_UDQM DRAM_BA0 DRAM_RAS DRAM_CKE DRAM_WE DRAM_D[0..15] SRAM_D[0..15] SD_CLK SD_CMD SD_DAT3 SD_DAT NCONFIG TMS TDI CONF_DONE NSTATUS NCE TCK ASDO DCLK NCSO TDO DATA0 LINK_D3 LINK_D0 LINK_D1 LINK_D2 VGA_CLOCK VGA_BLANK VGA_SYNC VGA_VS VGA_HS TD_RESET VGA_B[0..9] VGA_R[0..9] VGA_G[0..9] OTG_DACK1 OTG_DACK0 OTG_DREQ1 OTG_INT1 OTG_INT0 OTG_DREQ0 OTG_D[0..15] OTG_RESET OTG_LSPEED OTG_FSPEED OTG_CS OTG_A0 OTG_A1 OTG_OE OTG_WE TD_HS TD_VS 27MHz TD_D[0..7] TD_CLK27 TD_CLK27 Title Size Document Number Rev Date: Sheet of TOP LEVEL 2.0 ALTERA DE2 B Wednesday, August 02, 2006 3 24 Title Size Document Number Rev Date: Sheet of TOP LEVEL 2.0 ALTERA DE2 B Wednesday, August 02, 2006 3 24 Title Size Document Number Rev Date: Sheet of TOP LEVEL 2.0 ALTERA DE2 B Wednesday, August 02, 2006 3 24 USB DEVICE PAGE 22 OTG_WE OTG_OE OTG_RESET OTG_DACK0 OTG_DACK1 OTG_INT1 OTG_INT0 OTG_DREQ1 OTG_DREQ0 OTG_CS OTG_A1 OTG_A0 OTG_D[0..15] OTG_LSPEED OTG_FSPEED 12MHZ VIDEO PAGE 23-24 VGA_BLANK VGA_R[0..9] VGA_G[0..9] VGA_B[0..9] VGA_SYNC VGA_CLOCK VGA_HS VGA_VS TD_D[0..7] TD_HS TD_VS TD_RESET I2C_SCLK I2C_SDAT 27MHz TD_CLK27 ETHERNET PAGE 12 ENET_RESET 25MHZ ENET_CMD ENET_IOR ENET_IOW ENET_CS ENET_INT ENET_D[0..15] INPUT PAGE 13-17 GPIO_B[0..71] PS2_CLK PS2_DAT SW[0..17] UART_TXD UART_RXD KEY[0..3] 50MHZ EXT_CLOCK IRDA_TXD IRDA_RXD MEMORY PAGE 18-19 FLASH_RESET FLASH_WE FLASH_A[0..21] FLASH_CE FLASH_OE FLASH_D[0..7] DRAM_A[0..11] DRAM_LDQM DRAM_UDQM DRAM_CLK DRAM_CKE DRAM_BA0 DRAM_BA1 DRAM_D[0..15] DRAM_WE DRAM_CAS DRAM_RAS DRAM_CS SRAM_A[0..17] SRAM_D[0..15] SRAM_WE SRAM_CE SRAM_OE SD_CMD SD_DAT SD_CLK SRAM_UB SRAM_LB SD_DAT3 EP2S35 PAGE 7-11 NCONFIG TDI TMS TDO CONF_DONE NSTATUS TCK NCE ASDO DCLK NCSO DATA0 LED[5..26] SW[10..17] GPIO_B[0..71] FLASH_A[0..21] FLASH_D[0..7] SD_DAT SD_CLK SD_CMD HEX6_D[0..6] HEX4_D[0..6] HEX7_D[0..6] HEX5_D[0..6] KEY[0..3] SW[6..9] SRAM_CE SRAM_WE SRAM_A[0..17] SRAM_D[0..15] SRAM_OE FLASH_CE FLASH_OE FLASH_RESET FLASH_WE VGA_B[0..9] VGA_CLOCK VGA_R[0..9] VGA_G[0..9] VGA_BLANK VGA_SYNC TD_D[0..7] ENET_D[0..15] VGA_VS VGA_HS TD_RESET TD_HS TD_VS 27MHz ENET_RESET 25MHZ ENET_CMD ENET_INT LINK_D2 ENET_IOR ENET_IOW ENET_CS SD_DAT3 LINK_D3 AUD_XCK AUD_BCLK AUD_DACDAT AUD_DACLRCK AUD_ADCLRCK AUD_ADCDAT I2C_SCLK I2C_SDAT UART_RXD UART_TXD PS2_CLK PS2_DAT SW[3..5] LCD_D[0..7] LCD_WR LCD_EN LCD_RS LCD_BLON LCD_ON OTG_DREQ1 OTG_DREQ0 OTG_DACK1 OTG_DACK0 OTG_RESET OTG_INT1 OTG_INT0 HEX3_D[0..6] HEX2_D[0..6] HEX1_D[0..6] HEX0_D[0..6] OTG_CS OTG_OE OTG_WE OTG_A0 OTG_A1 OTG_D[0..15] SW[0..2] LED[0..4] DRAM_UDQM DRAM_LDQM DRAM_D[0..15] DRAM_BA1 DRAM_CS DRAM_BA0 DRAM_RAS DRAM_CKE DRAM_CAS DRAM_CLK DRAM_WE DRAM_A[0..11] 50MHZ EXT_CLOCK SRAM_UB SRAM_LB IRDA_TXD IRDA_RXD OTG_LSPEED OTG_FSPEED LINK_D0 LINK_D1 TD_CLK27 PWR PAGE 20 USB BLASTER PAGE 21 DATA0 NCSO DCLK ASDO TDO TMS TDI NCONFIG TCK CONF_DONE NCE NSTATUS LINK_D3 LINK_D0 LINK_D1 LINK_D2 12MHZ DISPLAY PAGE 5-6 HEX0_D[0..6] HEX1_D[0..6] HEX2_D[0..6] HEX3_D[0..6] HEX4_D[0..6] HEX5_D[0..6] HEX6_D[0..6] HEX7_D[0..6] LCD_BLON LCD_ON LCD_WR LCD_D[0..7] LCD_EN LCD_RS LED[0..26] AUDIO PAGE 4 AUD_BCLK AUD_DACDAT AUD_ADCLRCK AUD_DACLRCK AUD_ADCDAT I2C_SCLK I2C_SDAT AUD_XCK