TERASIC CYCLONE II EP2C35 Development Education BOARD HEMAT工 ONTENT PAGE TOP OVER PAGE TOP 01~03 AUDIO WM8731 04~04 DISPLAY LED SEGMENT EP2C35 EP2C35 BANK1.BANK8,POWER,CONFIG 07~11 ETHERNET DM9000A 工N/OUT CLOCK,PS2,RS232,KEY, SWITCH,CONNECT EMORY SRAM,DRAM,FLASH,SD CARD POWER POWER USB BLASTER USB BLASTER 21 1222 USBDEVICE I USB DEVICE 22 VIDEO ADV7181,ADV7123 ALTERA DE2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of COVER PAGE 2.0 ALTERA DE2 B Sunday, July 23, 2006 1 24 Title Size Document Number Rev Date: Sheet of COVER PAGE 2.0 ALTERA DE2 B Sunday, July 23, 2006 1 24 Title Size Document Number Rev Date: Sheet of COVER PAGE 2.0 ALTERA DE2 B Sunday, July 23, 2006 1 24 13 ~ 17 TOP 01 ~ 03 04 ~ 04 20 ~ 20 PAGE 05 ~ 06 12 ~ 12 SCHEMATIC TERASIC CYCLONE II EP2C35 Development & Education BOARD 18 ~ 19 CONTENT COVER PAGE , TOP AUDIO WM8731 DISPLAY LCD , LED , 7SEGMENT EP2C35 EP2C35 BANK1..BANK8 , POWER , CONFIG 07 ~ 11 ETHERNET DM9000A IN/OUT CLOCK , PS2 , RS232 , KEY , SWITCH , CONNECT MEMORY SRAM , DRAM , FLASH , SD CARD POWER POWER USB BLASTER USB BLASTER 21 ~ 21 22 ~ 22 23 ~ 24 USB DEVICE USB DEVICE VIDEO ADV7181 , ADV7123
RJ45 RS23 BLASTER DEVICE HOST OUT IN DECODER OUTPUT KEYBORAD ADV71 AD7123 DM9000A EP2C35 SD CARI EPCSI6 N IrDA SDRAM SRAM FLASH 面面 自自囱自自窗崮囱囱自自自囱自自囱自⊙◎ ALTERA DE2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A Title Size Document Number Rev Date: Sheet of PLACEMENT 2.0 ALTERA DE2 B Sunday, July 23, 2006 2 24 Title Size Document Number Rev Date: Sheet of PLACEMENT 2.0 ALTERA DE2 B Sunday, July 23, 2006 2 24 Title Size Document Number Rev Date: Sheet of PLACEMENT 2.0 ALTERA DE2 B Sunday, July 23, 2006 2 24 SW17 SW16 SW15 SW14 SW13 SW12 SW11 SW10 SW9 SW8 SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 USB BLASTER ISP1362 USB DEVICE USB HOST FT245 LCD MODULE LINE IN LINE OUT MIC IN WM8731 TV DECODER VGA OUTPUT RJ45 PS2 KEYBORAD DC RS232 9V SD CARD ADV7181 ADV7123 DM9000A M3128 EPCS16 EP2C35 SDRAM SRAM FLASH GPIO_0 GPIO_1 LEDR17 LEDR16 LEDR15 LEDR14 LEDR13 LEDR12 LEDR11 LEDR10 LEDR9 LEDR8 LEDR7 LEDR6 LEDR5 LEDR4 LEDR3 LEDR2 LEDR1 LEDR0 KEY3 KEY2 KEY1 KEY0 HEX7 HEX6 HEX5 HEX4 HEX3 HEX2 HEX1 HEX0 LEDG7 LEDG6 LEDG5 LEDG4 LEDG3 LEDG2 LEDG1 LEDG0 LEDR8 IrDA EXT CLK
0我15 SRAM D/a 15 以靠 a.71 鞋2睡 0
5 5 4 4 3 3 2 2 1 1 D D C C B B A A AUD_BCLK AUD_DACDAT AUD_DACLRCK LED[5..26] AUD_ADCLRCK I2C_SCLK AUD_XCK UART_TXD PS2_CLK LED[0..4] IRDA_TXD ENET_CMD ENET_IOR ENET_CS ENET_IOW ENET_INT ENET_D[0..15] 25MHZ ENET_RESET AUD_BCLK AUD_DACDAT AUD_ADCLRCK AUD_DACLRCK I2C_SCLK AUD_XCK AUD_ADCDAT I2C_SDAT HEX0_D[0..6] HEX1_D[0..6] HEX2_D[0..6] HEX3_D[0..6] HEX4_D[0..6] HEX5_D[0..6] HEX6_D[0..6] HEX7_D[0..6] LCD_D[0..7] LCD_BLON LCD_ON LCD_WR LCD_EN LCD_RS LED[0..26] PS2_DAT KEY[0..3] GPIO_B[0..71] SW[0..17] IRDA_TXD IRDA_RXD EXT_CLOCK 50MHZ PS2_CLK UART_TXD UART_RXD FLASH_A[0..21] DRAM_CLK DRAM_CKE DRAM_BA0 DRAM_BA1 SD_DAT DRAM_WE DRAM_CAS DRAM_RAS DRAM_CS SRAM_A[0..17] SD_DAT3 SD_CMD SD_CLK FLASH_CE FLASH_OE DRAM_D[0..15] DRAM_LDQM DRAM_UDQM NCSO ASDO DCLK TDI TMS TCK NCONFIG NCE CONF_DONE NSTATUS LINK_D0 LINK_D1 LINK_D2 OTG_INT1 OTG_INT0 OTG_DREQ1 OTG_DREQ0 OTG_WE OTG_OE OTG_RESET OTG_DACK0 OTG_DACK1 OTG_CS OTG_A1 OTG_A0 DATA0 TDO LINK_D3 12MHZ 12MHZ OTG_LSPEED OTG_FSPEED OTG_D[0..15] SRAM_D[0..15] DRAM_A[0..11] SRAM_WE SRAM_CE SRAM_OE SRAM_UB SRAM_LB FLASH_D[0..7] FLASH_RESET FLASH_WE TD_D[0..7] TD_HS 27MHz TD_VS TD_RESET I2C_SCLK I2C_SDAT VGA_BLANK VGA_SYNC VGA_CLOCK VGA_HS VGA_VS VGA_R[0..9] VGA_G[0..9] VGA_B[0..9] FLASH_D[0..7] 50MHZ UART_RXD PS2_DAT SW[0..2] EXT_CLOCK SW[3..5] SW[6..9] KEY[0..3] GPIO_B[0..71] SW[10..17] IRDA_RXD FLASH_CE FLASH_OE FLASH_RESET FLASH_WE FLASH_A[0..21] AUD_ADCDAT I2C_SDAT ENET_CMD ENET_RESET 25MHZ ENET_CS ENET_IOR ENET_IOW ENET_INT ENET_D[0..15] HEX6_D[0..6] HEX4_D[0..6] HEX5_D[0..6] HEX7_D[0..6] LCD_EN LCD_WR LCD_ON LCD_BLON LCD_RS LCD_D[0..7] HEX3_D[0..6] HEX2_D[0..6] HEX1_D[0..6] HEX0_D[0..6] SRAM_CE SRAM_WE SRAM_OE SRAM_UB SRAM_LB SRAM_A[0..17] DRAM_CS DRAM_BA1 DRAM_CAS DRAM_CLK DRAM_A[0..11] DRAM_LDQM DRAM_UDQM DRAM_BA0 DRAM_RAS DRAM_CKE DRAM_WE DRAM_D[0..15] SRAM_D[0..15] SD_CLK SD_CMD SD_DAT3 SD_DAT NCONFIG TMS TDI CONF_DONE NSTATUS NCE TCK ASDO DCLK NCSO TDO DATA0 LINK_D3 LINK_D0 LINK_D1 LINK_D2 VGA_CLOCK VGA_BLANK VGA_SYNC VGA_VS VGA_HS TD_RESET VGA_B[0..9] VGA_R[0..9] VGA_G[0..9] OTG_DACK1 OTG_DACK0 OTG_DREQ1 OTG_INT1 OTG_INT0 OTG_DREQ0 OTG_D[0..15] OTG_RESET OTG_LSPEED OTG_FSPEED OTG_CS OTG_A0 OTG_A1 OTG_OE OTG_WE TD_HS TD_VS 27MHz TD_D[0..7] TD_CLK27 TD_CLK27 Title Size Document Number Rev Date: Sheet of TOP LEVEL 2.0 ALTERA DE2 B Wednesday, August 02, 2006 3 24 Title Size Document Number Rev Date: Sheet of TOP LEVEL 2.0 ALTERA DE2 B Wednesday, August 02, 2006 3 24 Title Size Document Number Rev Date: Sheet of TOP LEVEL 2.0 ALTERA DE2 B Wednesday, August 02, 2006 3 24 USB DEVICE PAGE 22 OTG_WE OTG_OE OTG_RESET OTG_DACK0 OTG_DACK1 OTG_INT1 OTG_INT0 OTG_DREQ1 OTG_DREQ0 OTG_CS OTG_A1 OTG_A0 OTG_D[0..15] OTG_LSPEED OTG_FSPEED 12MHZ VIDEO PAGE 23-24 VGA_BLANK VGA_R[0..9] VGA_G[0..9] VGA_B[0..9] VGA_SYNC VGA_CLOCK VGA_HS VGA_VS TD_D[0..7] TD_HS TD_VS TD_RESET I2C_SCLK I2C_SDAT 27MHz TD_CLK27 ETHERNET PAGE 12 ENET_RESET 25MHZ ENET_CMD ENET_IOR ENET_IOW ENET_CS ENET_INT ENET_D[0..15] INPUT PAGE 13-17 GPIO_B[0..71] PS2_CLK PS2_DAT SW[0..17] UART_TXD UART_RXD KEY[0..3] 50MHZ EXT_CLOCK IRDA_TXD IRDA_RXD MEMORY PAGE 18-19 FLASH_RESET FLASH_WE FLASH_A[0..21] FLASH_CE FLASH_OE FLASH_D[0..7] DRAM_A[0..11] DRAM_LDQM DRAM_UDQM DRAM_CLK DRAM_CKE DRAM_BA0 DRAM_BA1 DRAM_D[0..15] DRAM_WE DRAM_CAS DRAM_RAS DRAM_CS SRAM_A[0..17] SRAM_D[0..15] SRAM_WE SRAM_CE SRAM_OE SD_CMD SD_DAT SD_CLK SRAM_UB SRAM_LB SD_DAT3 EP2S35 PAGE 7-11 NCONFIG TDI TMS TDO CONF_DONE NSTATUS TCK NCE ASDO DCLK NCSO DATA0 LED[5..26] SW[10..17] GPIO_B[0..71] FLASH_A[0..21] FLASH_D[0..7] SD_DAT SD_CLK SD_CMD HEX6_D[0..6] HEX4_D[0..6] HEX7_D[0..6] HEX5_D[0..6] KEY[0..3] SW[6..9] SRAM_CE SRAM_WE SRAM_A[0..17] SRAM_D[0..15] SRAM_OE FLASH_CE FLASH_OE FLASH_RESET FLASH_WE VGA_B[0..9] VGA_CLOCK VGA_R[0..9] VGA_G[0..9] VGA_BLANK VGA_SYNC TD_D[0..7] ENET_D[0..15] VGA_VS VGA_HS TD_RESET TD_HS TD_VS 27MHz ENET_RESET 25MHZ ENET_CMD ENET_INT LINK_D2 ENET_IOR ENET_IOW ENET_CS SD_DAT3 LINK_D3 AUD_XCK AUD_BCLK AUD_DACDAT AUD_DACLRCK AUD_ADCLRCK AUD_ADCDAT I2C_SCLK I2C_SDAT UART_RXD UART_TXD PS2_CLK PS2_DAT SW[3..5] LCD_D[0..7] LCD_WR LCD_EN LCD_RS LCD_BLON LCD_ON OTG_DREQ1 OTG_DREQ0 OTG_DACK1 OTG_DACK0 OTG_RESET OTG_INT1 OTG_INT0 HEX3_D[0..6] HEX2_D[0..6] HEX1_D[0..6] HEX0_D[0..6] OTG_CS OTG_OE OTG_WE OTG_A0 OTG_A1 OTG_D[0..15] SW[0..2] LED[0..4] DRAM_UDQM DRAM_LDQM DRAM_D[0..15] DRAM_BA1 DRAM_CS DRAM_BA0 DRAM_RAS DRAM_CKE DRAM_CAS DRAM_CLK DRAM_WE DRAM_A[0..11] 50MHZ EXT_CLOCK SRAM_UB SRAM_LB IRDA_TXD IRDA_RXD OTG_LSPEED OTG_FSPEED LINK_D0 LINK_D1 TD_CLK27 PWR PAGE 20 USB BLASTER PAGE 21 DATA0 NCSO DCLK ASDO TDO TMS TDI NCONFIG TCK CONF_DONE NCE NSTATUS LINK_D3 LINK_D0 LINK_D1 LINK_D2 12MHZ DISPLAY PAGE 5-6 HEX0_D[0..6] HEX1_D[0..6] HEX2_D[0..6] HEX3_D[0..6] HEX4_D[0..6] HEX5_D[0..6] HEX6_D[0..6] HEX7_D[0..6] LCD_BLON LCD_ON LCD_WR LCD_D[0..7] LCD_EN LCD_RS LED[0..26] AUDIO PAGE 4 AUD_BCLK AUD_DACDAT AUD_ADCLRCK AUD_DACLRCK AUD_ADCDAT I2C_SCLK I2C_SDAT AUD_XCK
PHONE JACK B sR6 47K47K 2K I2C ADDRESS READ IS 0x34 898 PHONE JACK P CVDD WM8731 1000P47K CLKOUT HPGND d C2 BC3 BC4 ALTERA DE2 nt Num be Tuesday July 25, 2006
5 5 4 4 3 3 2 2 1 1 D D C C B B A A AUD_BCLK AUD_DACDAT AUD_ADCLRCK AUD_DACLRCK AUD_ADCDAT I2C_SDAT I2C_SCLK AUD_XCK AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND VCC33VCC33 A_VCC33 A_VCC33 A_VCC33 A_VCC33 Title Size Document Number Rev Date: Sheet of AUDIO 2.0 ALTERA DE2 A Tuesday, July 25, 2006 4 24 Title Size Document Number Rev Date: Sheet of AUDIO 2.0 ALTERA DE2 A Tuesday, July 25, 2006 4 24 Title Size Document Number Rev Date: Sheet of AUDIO 2.0 ALTERA DE2 A Tuesday, July 25, 2006 4 24 I2C ADDRESS READ IS 0x34 I2C ADDRESS WRITE IS 0x35 LINE IN MIC IN LINE OUT BC3 0.1U R8 680 C1 1U TC1 100U/6.3V C2 1U R7 330 BC4 0.1U R11 47K C4 1000P C3 1U L 1 R 2 GND 3 NCR 4 NCL 5 J1 PHONE JACK P L 1 R 2 GND 3 NCR 4 NCL 5 J2 PHONE JACK B BC2 0.1U R10 47K R9 47K R6 4.7K R1 2K R5 4.7K BC1 0.1U R2 2K TC2 100U/6.3V BCLK 7 HPVDD 12 XTO 2 DCVDD 3 MBIAS 21 MICIN 22 RLINEIN 23 LLINEIN 24 MODE 25 CSB 26 SDIN 27 SCLK 28 ROUT 17 AVDD 18 AGND 19 VMID 20 LOUT 16 HPGND 15 RHPOUT 14 LHPOUT 13 XTI/MCLK 1 DGND 4 ADCLRCK 11 ADCDAT 10 DBVDD 5 CLKOUT 6 DACDAT 8 DACLRCK 9 U1 WM8731 R4 4.7K L 1 R 2 GND 3 NCR 4 NCL 5 J3 PHONE JACK G R3 4.7K C5 10U L1 BEAD
≮题 85883858出5 2 X 16 DIGIT LCD ALTERA DE2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A LED10 LED11 LED13 LED12 LED16 LED17 LED15 LED14 LED9 LED8 LED2 LED3 LED1 LED0 LED7 LED6 LED4 LED5 LED18 LED20 LED21 LED19 LED22 LED23 LED24 LED25 LED26 LCD_BL LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 LCD_CONT LCD_VCC LCD_BLON LCD_ON LCD_D[0..7] LCD_EN LCD_RS LED[0..26] LCD_WR VCC43 VCC43 VCC43 VCC5 Title Size Document Number Rev Date: Sheet of LCD AND LED 2.0 ALTERA DE2 B Tuesday, July 25, 2006 5 24 Title Size Document Number Rev Date: Sheet of LCD AND LED 2.0 ALTERA DE2 B Tuesday, July 25, 2006 5 24 Title Size Document Number Rev Date: Sheet of LCD AND LED 2.0 ALTERA DE2 B Tuesday, July 25, 2006 5 24 1 2 3 4 5 6 7 8 RN6 330 R16 1K 1 2 3 4 5 6 7 8 RN1 330 LEDR4 LEDR GND 1 VCC 2 CONT 3 RS 4 WR 5 EN 6 D0 7 D1 8 D2 9 D3 10 D4 11 D5 12 D6 13 D7 14 BL 15 GND 16 2 X 16 DIGIT LCD U2 LCD-2x16 LEDG1 LEDG Q5 8050 R17 47 LEDR5 LEDR LEDR6 LEDR LEDR7 LEDR R15 680 1 2 3 4 5 6 7 8 RN7 330 R14 680 Q3 8050 Q4 8550 LEDG6 LEDG LEDG0 LEDG LEDR1 LEDR LEDG3 LEDG LEDR9 LEDR C6 1U LEDR8 LEDR Q2 8550 1 2 3 4 5 6 7 8 RN2 330 LEDG8 LEDG Q1 8050 LEDR3 LEDR 1 2 3 4 5 6 7 8 RN3 330 LEDR14 LEDR LEDG5 LEDG LEDR15 LEDR LEDR16 LEDR LEDR17 LEDR LEDG2 LEDG LEDR0 LEDR 1 2 3 4 5 6 7 8 RN4 330 R13 680 LEDR10 LEDR R12 680 LEDR11 LEDR LEDR12 LEDR 1 2 3 4 5 6 7 8 RN5 330 LEDG7 LEDG LEDR13 LEDR LEDR2 LEDR LEDG4 LEDG
量暗 鞋主aF 鬟挂排 ALTERA DE2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A F7 F3 A3 F4 F0 HEX7_D0 HEX7_D1 HEX7_D2 HEX7_D3 HEX7_D4 HEX7_D5 HEX7_D6 HEX0_D4 HEX0_D3 HEX0_D2 HEX0_D6 HEX0_D1 HEX0_D5 HEX0_D0 HEX6_D0 HEX6_D1 HEX6_D2 HEX6_D3 HEX6_D4 HEX6_D5 HEX6_D6 HEX1_D5 HEX1_D4 HEX1_D3 HEX1_D6 HEX1_D2 HEX1_D1 HEX1_D0 HEX3_D6 HEX3_D5 HEX3_D0 HEX3_D4 HEX3_D3 HEX3_D2 HEX3_D1 HEX4_D5 HEX4_D4 HEX4_D3 HEX4_D0 HEX4_D2 HEX4_D1 HEX4_D6 HEX2_D0 HEX2_D1 HEX2_D2 HEX2_D3 HEX2_D4 HEX2_D5 HEX2_D6 HEX5_D6 HEX5_D1 HEX5_D5 HEX5_D4 HEX5_D3 HEX5_D2 HEX5_D0 C7 D7 B7 E7 A7 E0 B0 C0 A0 D0 B5 D5 E5 C5 A5 E2 B2 D2 C2 F2 G2 A2 E6 D6 A6 G6 F6 C6 B6 E4 D4 A4 C4 B4 E3 C3 B3 D3 E1 B1 G1 C1 F1 D1 A1 G7 F5 G5 G3 G4 G0 HEX0_D[0..6] HEX1_D[0..6] HEX2_D[0..6] HEX3_D[0..6] HEX4_D[0..6] HEX5_D[0..6] HEX6_D[0..6] HEX7_D[0..6] VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 Title Size Document Number Rev Date: Sheet of 7 SEGMENT 2.0 ALTERA DE2 B Sunday, July 23, 2006 6 24 Title Size Document Number Rev Date: Sheet of 7 SEGMENT 2.0 ALTERA DE2 B Sunday, July 23, 2006 6 24 Title Size Document Number Rev Date: Sheet of 7 SEGMENT 2.0 ALTERA DE2 B Sunday, July 23, 2006 6 24 1 2 3 4 5 6 7 8 RN20 330 1 2 3 4 5 6 7 8 RN18 330 1 2 3 4 5 6 7 8 RN21 330 1 2 3 4 5 6 7 8 RN19 330 1 2 3 4 5 6 10 9 8 7 e d dp c g b f a CA1 CA2 HEX5 7Segment Display e d dp c g b f a CA1 CA2 HEX5 7Segment Display 1 2 3 4 5 6 10 9 8 7 e d dp c g b f a CA1 CA2 HEX6 7Segment Display e d dp c g b f a CA1 CA2 HEX6 7Segment Display 1 2 3 4 5 6 7 8 RN10 330 1 2 3 4 5 6 10 9 8 7 e d dp c g b f a CA1 CA2 HEX4 7Segment Display e d dp c g b f a CA1 CA2 HEX4 7Segment Display 1 2 3 4 5 6 7 8 RN23 330 1 2 3 4 5 6 7 8 RN11 330 1 2 3 4 5 6 10 9 8 7 e d dp c g b f a CA1 CA2 HEX3 7Segment Display e d dp c g b f a CA1 CA2 HEX3 7Segment Display 1 2 3 4 5 6 10 9 8 7 e d dp c g b f a CA1 CA2 HEX2 7Segment Display e d dp c g b f a CA1 CA2 HEX2 7Segment Display 1 2 3 4 5 6 7 8 RN14 330 1 2 3 4 5 6 10 9 8 7 e d dp c g b f a CA1 CA2 HEX7 7Segment Display e d dp c g b f a CA1 CA2 HEX7 7Segment Display 1 2 3 4 5 6 7 8 RN12 330 1 2 3 4 5 6 7 8 RN15 330 1 2 3 4 5 6 10 9 8 7 e d dp c g b f a CA1 CA2 HEX0 7Segment Display e d dp c g b f a CA1 CA2 HEX0 7Segment Display 1 2 3 4 5 6 7 8 RN13 330 1 2 3 4 5 6 10 9 8 7 e d dp c g b f a CA1 CA2 HEX1 7Segment Display e d dp c g b f a CA1 CA2 HEX1 7Segment Display 1 2 3 4 5 6 7 8 RN16 330 1 2 3 4 5 6 7 8 RN22 330 1 2 3 4 5 6 7 8 RN17 330 1 2 3 4 5 6 7 8 RN8 330 1 2 3 4 5 6 7 8 RN9 330
罪 比a BANK1 K29 1tpCDPCLKT LVDS44p ENO outo ALTERA DE2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A LCD_D5 LCD_D4 OTG_D4 OTG_D3 OTG_D6 OTG_D2 LCD_D7 LCD_D3 LCD_D6 OTG_D9 OTG_D10 OTG_D14 OTG_D11 OTG_D12 OTG_D13 OTG_D8 OTG_D7 HEX6_D5 HEX6_D6 HEX7_D2 HEX7_D6 OTG_D15 HEX7_D4 HEX7_D5 HEX7_D3 HEX6_D3 HEX6_D4 OTG_D0 OTG_D1 OTG_D5 LCD_D0 LCD_D2 LCD_D1 SW11 SW12 HEX6_D1 HEX4_D3 HEX5_D5 HEX5_D4 HEX6_D0 HEX6_D2 HEX5_D6 DRAM_D15 DRAM_D13 DRAM_D14 DRAM_D9 DRAM_D10 DRAM_D11 DRAM_D12 DRAM_D7 DRAM_D8 SW13 DRAM_D5 DRAM_D6 DRAM_D4 DRAM_D1 DRAM_D2 DRAM_D3 DRAM_A11 DRAM_D0 DRAM_A10 DRAM_A9 DRAM_A8 DRAM_A6 DRAM_A5 DRAM_A7 DRAM_A1 DRAM_A2 DRAM_A3 DRAM_A4 DRAM_A0 SW17 SW14 SW15 SW16 HEX4_D1 HEX4_D2 HEX4_D0 HEX4_D5 HEX5_D3 HEX4_D6 HEX4_D4 HEX5_D0 HEX5_D2 HEX5_D1 SW10 HEX7_D0 HEX7_D1 HEX4_D[0..6] HEX5_D[0..6] HEX6_D[0..6] HEX7_D[0..6] DRAM_D[0..15] DRAM_A[0..11] DRAM_UDQM DRAM_LDQM DRAM_CLK DRAM_CKE DRAM_BA0 DRAM_BA1 DRAM_WE DRAM_CAS DRAM_RAS DRAM_CS 50MHZ LCD_WR LCD_EN LCD_RS LCD_BLON LCD_ON OTG_FSPEED OTG_A0 OTG_A1 OTG_CS OTG_WE OTG_OE OTG_RESET OTG_INT1 OTG_INT0 OTG_DREQ1 OTG_DREQ0 OTG_DACK1 OTG_DACK0 OTG_LSPEED OTG_D[0..15] SW[10..17] LCD_D[0..7] Title Size Document Number Rev Date: Sheet of EP2C35 BANK1 AND BANK 2 2.0 ALTERA DE2 B Sunday, July 23, 2006 7 24 Title Size Document Number Rev Date: Sheet of EP2C35 BANK1 AND BANK 2 2.0 ALTERA DE2 B Sunday, July 23, 2006 7 24 Title Size Document Number Rev Date: Sheet of EP2C35 BANK1 AND BANK 2 2.0 ALTERA DE2 B Sunday, July 23, 2006 7 24 PLL1_OUTn AA6 PLL1_OUTp AA7 IO1_3 AC3 LVDS0n AB4 LVDS0p AB3 LVDS1n AE3 LVDS1p AE2 LVDS2n AD3 LVDS2p AD2 LVDS3n Y5 LVDS4n AC1 LVDS4p AC2 LVDS5n AA3 LVDS5p AA4 LVDS6n AB1 LVDS6p AB2 VREFB1N1 W6 IO1_1 V7 LVDS7n T8 LVDS7p R8 LVDS8n Y4 LVDS8p Y3 LVDS9p AA2 LVDS9n AA1 LVDS10n V6 LVDS10p V5 IO1_2 Y1 W3 LVDS11n W4 LVDS11p/CDPCLK1 IO1_0 U5 LVDS15p T7 LVDS15n T6 LVDS14p V4 LVDS14n V3 W2 LVDS13p W1 LVDS13n LVDS12p U6 LVDS12n U7 LVDS16p V1 LVDS16n V2 LVDS17n U4 LVDS17p U3 LVDS18n U10 LVDS18p U9 LVDS19n U1 LVDS26p/DPCLK1 P3 LVDS26n P4 LVDS25p R2 LVDS25n R3 LVDS24p R4 LVDS24n R5 LVDS23p T10 LVDS23n T9 LVDS22p P7 LVDS22n P6 LVDS21p T2 LVDS21n T3 LVDS20p R6 LVDS20n R7 VREFB1N0 T4 LVDS19p U2 LVDS3p AA5 CLK3/LVDSCLK1n P1 CLK2/LVDSCLK1p P2 BANK1 U11A CYCLONE II EP2C35 CLK1/LVDSCLK0n N1 CLK0/LVDSCLK0p N2 LVDS27p/DPCLK0 M3 LVDS27n M2 LVDS28n M5 LVDS28p M4 IO2_4 L10 LVDS29n L3 LVDS29p L2 IO2_3 L9 LVDS30n L6 LVDS30p L7 LVDS31n P9 LVDS31p N9 VREFB2N1 L4 LVDS32n K2 LVDS32p K1 LVDS33n K3 LVDS33p K4 LVDS34n J1 LVDS34p J2 LVDS35n H1 LVDS35p H2 LVDS36n J4 LVDS36p J3 LVDS37n H4 LVDS37p H3 LVDS38n G2 LVDS38p/CDPCLK0 G1 LVDS39n F1 LVDS39p F2 LVDS40n K7 LVDS40p K8 IO2_2 J6 LVDS41n G3 LVDS41p G4 LVDS42n K5 LVDS42p K6 LVDS43n E1 LVDS43p E2 IO2_1 H6 LVDS44n J7 LVDS44p J8 VREFB2N0 J5 IO2_0 F7 LVDS45n D1 LVDS45p D2 LVDS46n F4 LVDS46p F3 LVDS47n G6 LVDS47p G5 LVDS48n C3 LVDS48p C2 PLL3_OUTn F6 PLL3_OUTp E5 LVDS49n/CLKUSR B3 LVDS49p/CRCERR B2 BANK2 U11B CYCLONE II EP2C35
BANK3 BA H 518 o72 ALTERA DE2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A SW7 TD_D5 TD_D1 TD_D7 TD_D0 TD_D6 TD_D2 VGA_G3 TD_D3 VGA_G2 VGA_R6 VGA_B4 VGA_B6 VGA_R5 VGA_G5 VGA_G9 VGA_B5 VGA_B3 VGA_B1 VGA_B7 VGA_B8 VGA_G4 VGA_G6 VGA_R7 VGA_R8 VGA_G0 VGA_R9 TD_D4 VGA_R0 VGA_R1 VGA_G7 VGA_G8 VGA_B2 VGA_G1 VGA_B0 VGA_R2 VGA_R4 VGA_B9 ENET_D0 ENET_D1 ENET_D2 ENET_D3 ENET_D4 ENET_D5 ENET_D6 ENET_D7 ENET_D8 ENET_D9 ENET_D10 ENET_D11 ENET_D12 ENET_D13 ENET_D14 ENET_D15 SW9 SW8 VGA_R3 VGA_B[0..9] VGA_CLOCK VGA_R[0..9] VGA_G[0..9] VGA_BLANK VGA_SYNC TD_D[0..7] ENET_D[0..15] VGA_VS VGA_HS TD_RESET TD_HS TD_VS 27MHz SW[7..9] ENET_IOW ENET_IOR ENET_CMD ENET_CS ENET_RESET ENET_INT AUD_XCK AUD_BCLK AUD_DACDAT AUD_ADCLRCK AUD_ADCDAT I2C_SDAT I2C_SCLK LINK_D3 LINK_D0 LINK_D1 LINK_D2 AUD_DACLRCK TD_CLK27 Title Size Document Number Rev Date: Sheet of EP2C35 BANK3 AND BANK 4 2.0 ALTERA DE2 B Wednesday, August 02, 2006 8 24 Title Size Document Number Rev Date: Sheet of EP2C35 BANK3 AND BANK 4 2.0 ALTERA DE2 B Wednesday, August 02, 2006 8 24 Title Size Document Number Rev Date: Sheet of EP2C35 BANK3 AND BANK 4 2.0 ALTERA DE2 B Wednesday, August 02, 2006 8 24 CLK9/LVDSCLK4p A13 CLK8/LVDSCLK4n B13 LVDS74p/DPCLK9 B14 LVDS74n A14 LVDS78p B16 IO4_0 D14 LVDS75p F14 LVDS75n G14 LVDS76p F13 LVDS76n G13 LVDS77p C15 LVDS78n C16 LVDS77n B15 LVDS79p D15 LVDS80p H15 LVDS79n E15 VREFB4N1 D16 LVDS80n H16 LVDS81p A17 LVDS81n B17 LVDS82p G15 LVDS82n F15 LVDS83p F16 LVDS83n G16 LVDS84p A18 LVDS84n B18 LVDS85p/DPCLK8 C17 LVDS85n D17 LVDS86p G17 LVDS86n F17 LVDS87p H17 LVDS87n J17 LVDS88p F18 LVDS88n G18 LVDS89p D18 LVDS89n E18 LVDS90p A19 LVDS90n B19 LVDS91p D19 LVDS91n C19 LVDS92p A20 LVDS92n B20 VREFB4N0 E20 IO4_1 D20 LVDS93p K16 LVDS93n J16 LVDS94p K17 LVDS94n J18 LVDS95p A21 LVDS95n B21 LVDS96p/CDPCLK6 B22 LVDS96n A22 LVDS97p A23 LVDS97n B23 LVDS98p D21 LVDS98n C21 LVDS99p C22 LVDS99n C23 BANK4 U11D CYCLONE II EP2C35 LVDS50p C6 LVDS51p A4 LVDS51n B4 LVDS52p A5 LVDS52n B5 LVDS53p/CDPCLK7 B6 LVDS53n A6 LVDS54p C4 LVDS54n D5 LVDS55p K9 LVDS55n J9 VREFB3N1 E8 IO3_3 H8 LVDS56p H10 LVDS56n G9 IO3_1 F9 LVDS57p D7 LVDS57n C7 IO3_0 D6 LVDS58p B7 LVDS58n A7 LVDS59p D8 LVDS59n C8 LVDS60p F10 LVDS60n G10 LVDS61p D9 LVDS61n C9 LVDS62p/DPCLK11 B8 LVDS62n A8 LVDS63p H11 LVDS63n H12 LVDS64p F11 LVDS64n E10 LVDS65p B9 LVDS65n A9 LVDS66p C10 LVDS66n D10 LVDS67p B10 LVDS70p F12 LVDS69n J14 LVDS67n A10 IO3_2 G11 VREFB3N0 D11 LVDS68p E12 LVDS69p J13 LVDS68n D12 LVDS70n G12 LVDS71p J10 LVDS71n J11 LVDS72p C11 LVDS72n B11 LVDS73p/DPCLK10 C12 LVDS73n B12 CLK11/LVDSCLK5p D13 CLK10/LVDSCLK5n C13 LVDS50n/DEV_CLRN C5 BANK3 U11C CYCLONE II EP2C35
BANK5 VDS1360 BANK6 LKTILY MDSCuKp Pea ETcIocx ALTERA DE2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A KEY2 SW2 GPIO_B2 GPIO_B3 GPIO_B5 GPIO_B4 GPIO_B8 GPIO_B9 GPIO_B7 GPIO_B6 GPIO_B13 GPIO_B11 GPIO_B15 GPIO_B14 GPIO_B12 GPIO_B10 GPIO_B1 GPIO_B0 KEY3 GPIO_B17 GPIO_B16 GPIO_B19 GPIO_B22 GPIO_B18 GPIO_B20 GPIO_B21 KEY0 GPIO_B24 GPIO_B25 GPIO_B26 GPIO_B27 GPIO_B28 GPIO_B29 GPIO_B31 GPIO_B30 GPIO_B32 GPIO_B33 GPIO_B34 GPIO_B23 GPIO_B50 GPIO_B49 GPIO_B48 GPIO_B51 GPIO_B47 GPIO_B52 GPIO_B54 GPIO_B53 GPIO_B55 GPIO_B56 GPIO_B57 GPIO_B58 GPIO_B59 GPIO_B60 GPIO_B61 GPIO_B62 GPIO_B63 GPIO_B64 GPIO_B65 GPIO_B66 GPIO_B67 GPIO_B68 GPIO_B69 HEX3_D4 HEX3_D0 HEX3_D1 HEX2_D6 HEX3_D3 HEX3_D2 HEX3_D5 HEX3_D6 GPIO_B70 GPIO_B71 SW0 SW1 KEY1 GPIO_B35 GPIO_B39 GPIO_B37 GPIO_B36 GPIO_B38 GPIO_B44 GPIO_B41 GPIO_B40 GPIO_B45 GPIO_B43 GPIO_B42 GPIO_B46 HEX1_D0 HEX2_D1 HEX1_D1 HEX2_D4 HEX1_D3 HEX1_D6 HEX1_D4 HEX1_D5 HEX2_D5 HEX1_D2 HEX2_D2 HEX2_D3 HEX2_D0 PS2_CLK UART_RXD PS2_DAT GPIO_B[36..71] HEX3_D[0..6] HEX1_D[0..6] HEX2_D[0..6] KEY[0..3] SW[0..2] UART_TXD 25MHZ SD_DAT SD_CLK SD_CMD EXT_CLOCK IRDA_TXD SD_DAT3 IRDA_RXD GPIO_B[0..35] Title Size Document Number Rev Date: Sheet of EP2C35 BANK5 AND BANK 6 2.0 ALTERA DE2 B Sunday, July 23, 2006 9 24 Title Size Document Number Rev Date: Sheet of EP2C35 BANK5 AND BANK 6 2.0 ALTERA DE2 B Sunday, July 23, 2006 9 24 Title Size Document Number Rev Date: Sheet of EP2C35 BANK5 AND BANK 6 2.0 ALTERA DE2 B Sunday, July 23, 2006 9 24 CLK6/LVDSCLK3p P25 CLK7/LVDSCLK3n P26 LVDS127p/DPCLK6 P23 LVDS127n P24 LVDS128p R25 LVDS128n R24 IO6_0 R20 LVDS129p T22 LVDS129n T23 LVDS130p R17 LVDS130n P17 LVDS131p T24 LVDS132n T17 VREFB6N0 T21 IO6_1 T20 LVDS133p U26 LVDS133n U25 LVDS134p U23 LVDS134n U24 LVDS135p R19 LVDS135n T19 LVDS136p U20 LVDS136n U21 LVDS137p V26 LVDS137n V25 LVDS138p V24 LVDS138n V23 W26 LVDS139p/CDPCLK4 W25 LVDS139n W23 LVDS140p W24 LVDS140n IO6_2 U22 LVDS141p Y25 LVDS141n Y26 LVDS142p AA26 LVDS142n AA25 LVDS143p Y23 LVDS143n Y24 LVDS144p AB25 LVDS144n AB26 LVDS145p AC26 LVDS145n AC25 VREFB6N1 V22 LVDS146p AB23 LVDS146n AB24 LVDS147p AA23 LVDS147n AA24 LVDS148p Y22 LVDS148n W21 LVDS131n T25 LVDS132p T18 PLL4_OUTp V21 PLL4_OUTn V20 IO6_3 Y21 LVDS149p AD24 LVDS149n AD25 IO6_4 AC23 LVDS150p/nCEO AE24 LVDS150n/INIT_DONE AE25 BANK6 U11F CYCLONE II EP2C35 PLL2_OUTn F20 PLL2_OUTp F21 LVDS100p E22 LVDS100n D23 LVDS101p G21 LVDS101n G22 IO5_1 H21 LVDS102p E23 LVDS102n E24 LVDS103p B24 LVDS103n B25 LVDS104p C25 LVDS104n C24 VREFB5N0 J22 LVDS106p E26 LVDS106n E25 LVDS107p F24 LVDS107n F23 LVDS108p J21 LVDS108n J20 LVDS109p F25 LVDS109n F26 LVDS110p N18 LVDS110n P18 LVDS111p G23 LVDS111n G24 IO5_3 K22 LVDS112p/CDPCLK5 G25 LVDS112n G26 LVDS113p H23 LVDS113n H24 LVDS114p J23 LVDS114n J24 LVDS115p H25 LVDS115n H26 IO5_0 H19 LVDS116p K18 LVDS116n K19 IO5_2 K21 LVDS117p K23 LVDS117n K24 LVDS118p L21 LVDS118n L20 LVDS119p J25 LVDS119n J26 VREFB5N1 L23 LVDS120p L24 LVDS120n L25 IO5_4 L19 LVDS121p K25 LVDS121n K26 LVDS122p M22 LVDS122n M23 LVDS123p M19 LVDS123n M20 LVDS124p N20 LVDS124n M21 LVDS125p M24 LVDS125n M25 LVDS105p D26 LVDS105n D25 LVDS126p/DPCLK7 N23 LVDS126n N24 CLK4/LVDSCLK2p N25 CLK5/LVDSCLK2n N26 BANK5 U11E CYCLONE II EP2C35
BANK8 VREFETNO ALTERA DE2
5 5 4 4 3 3 2 2 1 1 D D C C B B A A SW3 SW4 SW5 SW6 FLASH_A2 FLASH_A0 FLASH_A1 FLASH_A11 FLASH_A7 FLASH_A8 FLASH_A10 FLASH_A5 FLASH_A9 FLASH_A6 FLASH_A4 FLASH_A3 FLASH_A12 FLASH_A20 FLASH_A14 FLASH_A17 FLASH_A15 FLASH_A16 FLASH_A19 FLASH_A21 FLASH_A18 FLASH_A13 HEX0_D6 HEX0_D3 HEX0_D1 HEX0_D5 HEX0_D0 HEX0_D4 HEX0_D2 SRAM_A14 SRAM_A16 SRAM_D10 SRAM_A17 SRAM_D8 SRAM_D6 SRAM_D2 SRAM_D11 SRAM_A9 SRAM_D9 SRAM_A0 SRAM_A4 SRAM_D12 SRAM_D1 SRAM_D0 SRAM_A1 SRAM_D13 SRAM_A6 SRAM_A12 SRAM_D14 SRAM_A7 SRAM_A10 SRAM_D15 SRAM_D4 SRAM_A3 SRAM_A5 SRAM_D3 SRAM_D5 SRAM_A2 SRAM_A13 SRAM_A11 SRAM_D7 SRAM_A15 SRAM_A8 FLASH_D7 FLASH_D6 FLASH_D5 FLASH_D4 FLASH_D3 FLASH_D2 FLASH_D1 FLASH_D0 LED0 LED3 LED2 LED1 LED4 LED5 LED24 LED22 LED19 LED23 LED25 LED20 LED21 LED26 LED6 LED7 LED12 LED11 LED10 LED9 LED8 LED13 LED15 LED14 LED17 LED18 LED16 LED[0..26] SW[3..6] SRAM_D[0..15] FLASH_CE FLASH_A[0..21] FLASH_OE FLASH_RESET FLASH_WE SRAM_A[0..17] HEX0_D[0..6] SRAM_UB SRAM_LB SRAM_WE SRAM_CE SRAM_OE FLASH_D[0..7] Title Size Document Number Rev Date: Sheet of EP2C35 BANK7 AND BANK 8 2.0 ALTERA DE2 B Sunday, July 23, 2006 10 24 Title Size Document Number Rev Date: Sheet of EP2C35 BANK7 AND BANK 8 2.0 ALTERA DE2 B Sunday, July 23, 2006 10 24 Title Size Document Number Rev Date: Sheet of EP2C35 BANK7 AND BANK 8 2.0 ALTERA DE2 B Sunday, July 23, 2006 10 24 LVDS151n AE23 LVDS151p AF23 LVDS152n AB21 LVDS152p AC22 LVDS153n AD22 LVDS153p AD23 LVDS154n AD21 LVDS154p/CDPCLK3 AC21 LVDS155n AE22 LVDS155p AF22 LVDS156n W19 LVDS156p V18 LVDS157n U18 LVDS157p U17 IO7_0 AA20 VREFB7N0 Y18 LVDS158n AE21 LVDS158p AF21 LVDS159n AC20 LVDS159p AB20 LVDS160n AE20 LVDS160p AF20 LVDS161n AC19 LVDS161p AD19 LVDS162n AA18 LVDS162p AA17 LVDS163n V17 W17 LVDS163p LVDS164n AC18 LVDS164p AB18 LVDS165n AE19 LVDS165p/DPCLK5 AF19 LVDS166n AE18 LVDS166p AF18 LVDS167n Y16 LVDS167p AA16 LVDS168n AD17 LVDS168p AC17 LVDS169n AE17 LVDS169p AF17 W16 LVDS170n W15 LVDS170p VREFB7N1 AC16 LVDS171n AD16 LVDS171p AE16 LVDS172n AC15 LVDS172p AB15 LVDS173n AA15 LVDS173p Y15 LVDS174n Y14 LVDS174p AA14 LVDS175n Y13 LVDS175p AA13 IO7_1 AC14 LVDS176n AD15 LVDS176p AE15 CLK12/LVDSCLK6n AE14 CLK13/LVDSCLK6p AF14 BANK7 CYCLONE II EP2C35 U11G CLK14/LVDSCLK7n AD13 CLK15/LVDSCLK7p AC13 LVDS177n AF13 LVDS177p/DPCLK3 AE13 LVDS178n AE12 LVDS178p AD12 LVDS179n Y12 LVDS179p AA12 LVDS180n U12 LVDS180p V11 LVDS181n V13 LVDS181p V14 LVDS182n AE11 LVDS182p AD11 VREFB8N0 AC12 IO8_3 AB12 LVDS183n AF10 LVDS183p AE10 LVDS184n AC11 LVDS184p AD10 LVDS185n AF9 LVDS185p AE9 LVDS186n AC10 LVDS186p AC9 W12 LVDS187n W11 LVDS187p LVDS188n AF8 LVDS188p/DPCLK2 AE8 LVDS189n AF7 LVDS189p AE7 LVDS190n Y11 LVDS190p AA11 LVDS191n AB10 LVDS191p AA10 IO8_1 AA9 LVDS192n AF6 LVDS192p AE6 LVDS193n AD8 LVDS193p AC8 IO8_2 AB8 LVDS194n Y10 W10 LVDS194p IO8_0 W8 VREFB8N1 AC7 LVDS195n V9 LVDS195p V10 LVDS196n AD7 LVDS196p AD6 LVDS197n AF5 LVDS197p AE5 LVDS198n AD5 LVDS198p AD4 LVDS199n AC6 LVDS199p AC5 LVDS200p AF4 LVDS200n/DEV_OE AE4 BANK8 CYCLONE II EP2C35 U11H
