System tasks:Simulation Control module test_moore_detector; reg x=0,reset=1,clock=0; wire z; initial moore_detector MUT (x,reset,clock,z); begin initial #24 reset=1'b0; #24 reset=1'b0; always #5 clock=~clock; #165 $finish; always #7X=~X; end Initial #189$stop; always #5 clock=~clock; endmodule always #7 x=~x; The first time the flow of a The first time the flow of a procedural block reaches $stop at procedural block reaches Sfinish 189 ns,simulation stops. at 189 ns,simulation terminates. A stopped simulation can be resumed. A finished simulation cannot be resumed. 2021/1/13 ASIC Design,by Yan Bo 15ASIC Design, by Yan Bo 15 System tasks: Simulation Control module test_moore_detector; reg x=0, reset=1, clock=0; wire z; moore_detector MUT ( x, reset, clock, z ); endmodule initial #24 reset=1'b0; always #5 clock=~clock; always #7 x=~x; Initial #189 $stop; The first time the flow of a procedural block reaches $stop at 189 ns, simulation stops. A stopped simulation can be resumed. initial begin #24 reset=1'b0; #165 $finish; end always #5 clock=~clock; always #7 x=~x; The first time the flow of a procedural block reaches $finish at 189 ns, simulation terminates. A finished simulation cannot be resumed. 2021/1/13