MICROCHIPENC28J60Data SheetStand-Alone Ethernet Controllerwith SPI InterfacePreliminaryDS39662C@2008 Microchip Technology Inc
© 2008 Microchip Technology Inc. Preliminary DS39662C ENC28J60 Data Sheet Stand-Alone Ethernet Controller with SPI Interface
NotethefollowingdetailsofthecodeprotectionfeatureonMicrochipdevices:Microchip products meet the specification contained in their particular Microchip Data Sheet.Microchip believes that itsfamily of products is oneofthemostsecurefamilies of its kind on themarkettoday,when used intheintendedmannerandundernormalconditionsThere are dishonest and possibly llegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's DataSheets. Most likely, the person doing so is engaged in theft of intellectual property.Microchip is willing to workwith thecustomerwho is concernedabout the integrity of theircode.Neither Microchip nor anyother semiconductormanufacturer can guarantee the security of their code.Code protection does notmean that we are guaranteeing the product as"unbreakable."Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Information contained in this publication regarding deviceTrademarksapplications and the like is provided only for your convenienceThe Microchip name and logo, the Microchip logo, Accuron,and may be superseded by updates. It is your responsibility todsPIC,KEELoQ,KEELoQlogo,MPLAB,PIC,PICmicroensure that your application meets with your specifications.PICSTART,PRO MATE, rfPIC and SmartShunt are registeredMICROCHIPMAKESNOREPRESENTATIONSORtrademarks of Microchip Technology Incorporated in theWARRANTIES OF ANY KIND WHETHER EXPRESSORU.S.A. and other countries.IMPLIED,WRITTENORORALSTATUTORYORFilterLab, Linear Active Thermistor, MXDEV, MXLAB,OTHERWISE,RELATEDTOTHEINFORMATION,SEEVAL,SmartSensorandTheEmbeddedControlSolutionsINCLUDING BUTNOTLIMITEDTOITSCONDITION,Company are registered trademarks of Microchip TechnologyQUALITY,PERFORMANCE,MERCHANTABILITYORIncorporated in the U.S.A.FITNESS FOR PURPOSE.Microchip disclaims all liabilityarising from this information and its use. Use of MicrochipAnalog-for-the-Digital Age, Application Maestro, CodeGuard,devices inlifesupportand/orsafetyapplications isentirelyatdsPICDEM, dsPICDEM.net,dsPICworks, dsSPEAK,ECAN,thebuyer's risk,andthebuyeragreesto defend,indemnifyandECONOMONITOR,FanSense, In-Circuit SerialholdharmlessMicrochipfromanyandalldamages,claims,Programming,ICSP,ICEPIC,Mindi,MiWi,MPASM,MPLABsuits,orexpensesresultingfromsuchuse.NolicensesareCertified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,conveyed, implicitly or otherwise,under any MicrochipPICDEM.net, PICtail, PIC32 logo,PowerCal, Powerlnfointellectual property rights.PowerMate,PowerTool, REALICE,rfLAB,Select Mode,TotalEndurance, UNI/O,WiperLock and ZENA are trademarks ofMicrochip Technology Incorporated in the U.S.A. and othercountries.SQTPis a service mark of MicrochipTechnology Incorporatedin the U.S.AAll other trademarks mentioned herein are property of theirrespectivecompanies. 2008, Microchip Technology Incorporated, Printed in theU.S.A.,AllRightsReserved.6 Printed on recycled paper.Microchip received ISO/TS-16949:2002 certification for its worldwideheadquarters,design andwaferfabrication facinties in ChandlerandQUALITYMANAGEMENTSYSTEMTempe,Arizona,Gresham,Oregon anddesign centers in Califomiaand India.The Company'squality system processes andproceduresCERTIFIEDBYDNVareforitsPICMCUsanddsPICDSCs,KEELoqcodehoppingdevices, Serial EEPROMs,microperipherals, nonvolatilememory andanalogproducts.In addition,Microchip's quality systemforthe desigrIS0/TS16949:2002andmanufactureofdevelopmentsystemsis/S09001:2000certifiedPreliminaryDS39662C-page ii@ 2008 Microchip Technology Inc
DS39662C-page ii Preliminary © 2008 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyerís risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: ï Microchip products meet the specification contained in their particular Microchip Data Sheet. ï Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. ï There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchipís Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. ï Microchip is willing to work with the customer who is concerned about the integrity of their code. ï Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as ìunbreakable.î Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchipís code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Companyís quality system processes and procedures are for its PICÆ MCUs and dsPICÆ DSCs, KEELOQÆ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchipís quality system for the design and manufacture of development systems is ISO 9001:2000 certified
ENC28J60MICROCHIPStand-Alone Ethernet Controller with SPIInterfaceEthernetControllerFeaturesOperational.IEEE802.3TMCompatibleEthernetController.SixInterruptSources and OneInterruptOutputPin:FullyCompatiblewith10/100/1000Base-TNetworks.25MHzClockInputRequirement:IntegratedMAC and10Base-TPHY·ClockOutPinwithProgrammablePrescaler.SupportsOne10Base-TPortwithAutomatic.OperatingVoltageof3.1Vto3.6V(3.3Vtypical)Polarity Detection and Correction.5VTolerantInputs.Supports Full and Half-Duplexmodes.TemperatureRange:-40°C to+85°C Industrial,:ProgrammableAutomaticRetransmitonCollision0°Cto+70CCommercial (SSOPonly)·ProgrammablePaddingand CRCGeneration·28-PinSPDIP,SSOP,SOIC,QFNPackagProgrammableAutomaticRejectionofErroneous.PacketsPackageTypes·SPI InterfacewithClock Speeds Upto20MHz28-PinSPDIP,SSOP,SOIC-128VDDBufferVCAP277口+LEDAVss口226-93.8-KbyteTransmit/ReceivePacketDualPortSRAMCLKOUTLEDB25 巨94INTVDDOSC·ConfigurableTransmit/ReceiveBufferSize2445ENC28J60+OSC2NC*·Hardware Managed CircularReceive FIFOso.D6OSC1SI227VSSOSC.Byte-WideRandomandSequentialAccesswith21ESCK-98VSSPLLAuto-IncrementCS20巨-9VDDPLL:InternalDMAforFastDataMovementRESET1019VDDRX18VSSRX~11VSSTX.HardwareAssistedChecksumCalculationfor招TPIN-+12TPOUT+VariousNetworkProtocolsTPIN++13TPOUT-14156RBIASVDDTXMediumAccessController(MAC)Features中电购28-pinQFN.SupportsUnicast, MulticastandBroadcastA3Packets:Programmable Receive Packet Filtering and Wake-upHoston Logical AND or ORof the Following:H-Unicastdestinationaddress28 27 26 25 24 23 22-MulticastaddressVDDOSC21日NC*120OSC22BroadcastaddressSO-年319巨OSC1SI--MagicPacketmENC28J604418VssOSCSCK-Groupdestinationaddresses as definedby75VSSPLLcs-年6VDDPLLRESET-64-bitHashTable15年7VDDRXVSSRXProgrammable Pattern Matching ofup to.89101112131464bytesatuser-defined offsetPhysicalLayer(PHY)Features:LoopbackmodeRB0.Two Programmable LED Outputs for LINK, TX,RX,CollisionandFull/Half-DuplexStatus*Reserved pin; always leave disconnected.PreliminaryDS39662C-page12008MicrochipTechnologyInc
© 2008 Microchip Technology Inc. Preliminary DS39662C-page 1 ENC28J60 Ethernet Controller Features ï IEEE 802.3ô Compatible Ethernet Controller ï Fully Compatible with 10/100/1000Base-T Networks ï Integrated MAC and 10Base-T PHY ï Supports One 10Base-T Port with Automatic Polarity Detection and Correction ï Supports Full and Half-Duplex modes ï Programmable Automatic Retransmit on Collision ï Programmable Padding and CRC Generation ï Programmable Automatic Rejection of Erroneous Packets ï SPI Interface with Clock Speeds Up to 20 MHz Buffer ï 8-Kbyte Transmit/Receive Packet Dual Port SRAM ï Configurable Transmit/Receive Buffer Size ï Hardware Managed Circular Receive FIFO ï Byte-Wide Random and Sequential Access with Auto-Increment ï Internal DMA for Fast Data Movement ï Hardware Assisted Checksum Calculation for Various Network Protocols Medium Access Controller (MAC) Features ï Supports Unicast, Multicast and Broadcast Packets ï Programmable Receive Packet Filtering and Wake-up Host on Logical AND or OR of the Following: - Unicast destination address - Multicast address - Broadcast address - Magic Packetô - Group destination addresses as defined by 64-bit Hash Table - Programmable Pattern Matching of up to 64 bytes at user-defined offset Physical Layer (PHY) Features ï Loopback mode ï Two Programmable LED Outputs for LINK, TX, RX, Collision and Full/Half-Duplex Status Operational ï Six Interrupt Sources and One Interrupt Output Pin ï 25 MHz Clock Input Requirement ï Clock Out Pin with Programmable Prescaler ï Operating Voltage of 3.1V to 3.6V (3.3V typical) ï 5V Tolerant Inputs ï Temperature Range: -40°C to +85°C Industrial, 0°C to +70°C Commercial (SSOP only) ï 28-Pin SPDIP, SSOP, SOIC, QFN Packages Package Types ENC28J60 28-Pin SPDIP, SSOP, SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 OSC2 OSC1 LEDA LEDB TPINTPIN+ INT NC* 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 ENC28J60 11 12 13 14 18 17 16 15 VDDOSC VDDTX TPOUT+ TPOUT- 28-pin QFN RESET CS SO SI SCK RBIAS VSSRX CLKOUT VCAP VDDRX VSSOSC VDDPLL VSSPLL VSSTX VDD VSS VCAP OSC2 OSC1 VDDRX VSSTX TPOUT+ TPOUTLEDA LEDB VDDOSC VSSOSC VDDTX VDDPLL VSSPLL CLKOUT RESET CS SO SI TPIN+ TPINRBIAS INT NC* SCK VDD VSS VSSRX * Reserved pin; always leave disconnected. Stand-Alone Ethernet Controller with SPI Interface
ENC28J60TableofContents1.0Overview...32.0External Connections53.011MemoryOrganization..4.0Serial Peripheral Interface (SPI)255.031EthernetOverview.6.033Initialization.....7.0TransmittingandReceivingPackets398.047Receive Filters...9.053DuplexModeConfigurationandNegotiation.5510.0FlowControl11.0Reset.596312.0 Interrupts.13.0 DirectMemoryAccessController7114.0Power-Down...737515.0Built-inSelf-TestController16.0 ElectricalCharacteristics7917.0 PackagingInformation.8389Appendix A: Revision History.TheMicrochip Web Site.9191CustomerChangeNotificationServiceCustomerSupport9192ReaderResponse93IndexProduct Identification System..95TOOURVALUEDCUSTOMERSIt is our intention toprovide ourvalued customers withthebestdocumentation possibleto ensuresuccessful useofyour Microchipproducts.Tothis end,wewill continueto improveourpublications to better suit your needs.Our publications willberefined andenhancedasnewvolumesandupdatesareintroduced.If youhaveanyquestionsorcomments regardingthispublication,pleasecontacttheMarketingCommunicationsDepartmentviaE-mail atdocerrors@microchip.com orfax the Reader ResponseForm in theback of this data sheetto(480)792-4150.Wewelcomeyourfeedback.Most CurrentDataSheetTo obtain the most up-to-date version of this data sheet, please registerat our Worldwide Web site at:http:/www.microchip.comYoucandetermine theversionofa data sheetbyexamining its literaturenumberfound on thebottom outsidecornerof anypage.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).ErrataAnerratasheet,describingminoroperationaldifferencesfromthedatasheetandrecommendedworkarounds,mayexistforcurrentdevices.Asdevice/documentationissuesbecomeknowntous,wewillpublishanerratasheet.TheerratawillspecifytherevisionofsiliconandrevisionofdocumenttowhichitappliesTodetermineif an errata sheet exists fora particulardevice,pleasecheck withoneof thefollowing:.Microchip'sWorldwideWebsite:http://www.microchip.comYourlocalMicrochipsalesoffice(seelastpage)Whencontactingasalesofficepleasespecifywhichdevice,revisionofsiliconanddata sheet (includeliteraturenumber)youareusingCustomerNotificationSystemRegisteron ourweb siteat www.microchip.comto receive themost current information on allof our products.PreliminaryDS39662C-page2?2008 Microchip Technology Inc
ENC28J60 DS39662C-page 2 Preliminary © 2008 Microchip Technology Inc. Table of Contents 1.0 Overview . 3 2.0 External Connections . 5 3.0 Memory Organization . 11 4.0 Serial Peripheral Interface (SPI). 25 5.0 Ethernet Overview. 31 6.0 Initialization. 33 7.0 Transmitting and Receiving Packets . 39 8.0 Receive Filters. 47 9.0 Duplex Mode Configuration and Negotiation. 53 10.0 Flow Control . 55 11.0 Reset . 59 12.0 Interrupts . 63 13.0 Direct Memory Access Controller. 71 14.0 Power-Down. 73 15.0 Built-in Self-Test Controller . 75 16.0 Electrical Characteristics . 79 17.0 Packaging Information. 83 Appendix A: Revision History. 89 The Microchip Web Site . 91 Customer Change Notification Service . 91 Customer Support. 91 Reader Response . 92 Index . 93 Product Identification System. 95 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: ï Microchipís Worldwide Web site; http://www.microchip.com ï Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products
ENC28J601.0OVERVIEWThe ENC28J60 consists of seven major functionalblocks:The ENC28J60 is a stand-alone Ethernet controller1.AnSPlinterfacethatservesasacommunica-withan industry standard SerialPeripheral Interfacetionchannelbetween thehostcontrollerand the(SPl). It is designed to serve as an Ethernet networkENC28J60.interface for any controller equipped with SPl.2.Control registers which are used to controlandTheENC28J60meetsalloftheIEEE802.3specifica-monitortheENC28J60.tions.It incorporates a number of packet filtering3.A dual port RAM buffer for received andschemestolimitincomingpackets.Italsoprovidesantransmitteddatapacketsintemal DMAmoduleforfastdata throughput andhard-bAnarbiterto control theaccessto theRAMware assisted checksum calculation, which is used inbuffer whenrequests are madefrom DMA,variousnetworkprotocols.Communicationwiththetransmitandreceiveblocks.hostcontrollerisimplementedviaaninterruptpinand6The bus interface that interpretsdataandtheSPl,withclockratesofupto20MHz.Twocommandsreceived via the SPIinterface.dedicated pins are used for LED link and networkactivityindication6.The MAC (MediumAccess Control) module thatimplementsIEEE802.3compliantMAClogic.AsimpleblockdiagramoftheENC28J60isshownin7.The PHY (Physical Layer) module that encodesFigure 1-1.Atypical application circuit using the deviceand decodes the analogdata that is present onisshowninFigure1-2.WiththeENC28J60,twopulsethe twisted-pair interfacetransformersandafewpassivecomponents areall thatarerequiredtoconnectamicrocontrollertoanEthernetThedevicealsocontainsothersupportblocks,suchasnetwork.theoscillator,on-chipvoltageregulator,leveltranslatorstoprovide5Vtolerant/Osandsystemcontrol logicFIGURE1-1:ENC28J60BLOCKDIAGRAM繁BufferRX8KbytesMACDual PortRAMERXBMRXF (Filter)TXMIIchoInterfaceCLKOUTDMA&ControlArbiterChecksumμchoRegistersPHYTPIN+ch1TXchRX窗TXBMINTFlowControlBus InterfaceMIMRBIASInterface区HostInterface脑呕呕脑25MHzSPIVoltagePower-onOSC2System ControlOscillatorRegulatorReset区+卤卤VCAPRESET(1)Note 1:Thesepins are5Vtolerant.Preliminary@2008 Microchip Technology Inc.DS39662C-page 3
© 2008 Microchip Technology Inc. Preliminary DS39662C-page 3 ENC28J60 1.0 OVERVIEW The ENC28J60 is a stand-alone Ethernet controller with an industry standard Serial Peripheral Interface (SPI). It is designed to serve as an Ethernet network interface for any controller equipped with SPI. The ENC28J60 meets all of the IEEE 802.3 specifications. It incorporates a number of packet filtering schemes to limit incoming packets. It also provides an internal DMA module for fast data throughput and hardware assisted checksum calculation, which is used in various network protocols. Communication with the host controller is implemented via an interrupt pin and the SPI, with clock rates of up to 20 MHz. Two dedicated pins are used for LED link and network activity indication. A simple block diagram of the ENC28J60 is shown in Figure 1-1. A typical application circuit using the device is shown in Figure 1-2. With the ENC28J60, two pulse transformers and a few passive components are all that are required to connect a microcontroller to an Ethernet network. The ENC28J60 consists of seven major functional blocks: 1. An SPI interface that serves as a communication channel between the host controller and the ENC28J60. 2. Control registers which are used to control and monitor the ENC28J60. 3. A dual port RAM buffer for received and transmitted data packets. 4. An arbiter to control the access to the RAM buffer when requests are made from DMA, transmit and receive blocks. 5. The bus interface that interprets data and commands received via the SPI interface. 6. The MAC (Medium Access Control) module that implements IEEE 802.3 compliant MAC logic. 7. The PHY (Physical Layer) module that encodes and decodes the analog data that is present on the twisted-pair interface. The device also contains other support blocks, such as the oscillator, on-chip voltage regulator, level translators to provide 5V tolerant I/Os and system control logic. FIGURE 1-1: ENC28J60 BLOCK DIAGRAM Dual Port RAM 8 Kbytes DMA & Checksum TXBM RXBM Arbiter Flow Control Host Interface Control Registers 25 MHz Power-on PHY Bus Interface SPI MII Interface MIIM Interface TPOUT+ TPOUTTPIN+ TPINTX RX RBIAS OSC1 Voltage OSC2 System Control CS(1) SI(1) SO SCK(1) INT VCAP CLKOUT LEDA LEDB RESET(1) RXF (Filter) RX TX MAC ch0 ch1 ch0 ch1 Buffer Note 1: These pins are 5V tolerant. Reset Regulator Oscillator
ENC28J60FIGURE 1-2:TYPICALENC28J60-BASEDINTERFACEMCUENC28J60TPIN+/-18年54RJ45VO美TPOUT+/-SDO1soSDI4ETHERNETSCKTRANSFORMERTX/RXSCKMACPHYBuffer0INTLEDAINTX4福LEDBTABLE 1-1:PINOUTIODESCRIPTIONSPin NumberPinBufferPin NameDescriptionSPDIP,TypeTypeQFNSOIC,SSOP1P25VCAP2.5V output from internal regulator.A lowEquivalentSeries Resistance(ESR)capacitor,witha typical valueof10mFanda minimum value of1mF toground, must be placed on this pin.226PVss1Ground referenceProgrammable clock output pin(1)CLKOUT3270一40INT interrupt output pin,(2)INT28一NC510-Reservedfunction;always leaveunconnected.620soData out pin for SPI interface.(2)-7SI31STData in pin for SPI interface(3)84Clock in pin for SPIinterface.(3)SCK1STcs951STChip select input pin for SPI interface(3,4)106一Active-lowdeviceResetinput,(3,4)RESETST7PVSSRX11-Ground referencefor PHY RX1281ANATPIN-Differential signal input.9TPIN+13-ANADifferential signal input.10RBIAS141ANABias current pin for PHY.Mustbe tied to groundvia a resistor (refertoSection2.4"Magnetics,Termination and OtherExternal Components"for details).P1511VDDTXPositivesupplyforPHYTX16120TPOUT-一Differential signal output.17130TPOUT+一Differential signaloutput.14PVSSTX18一Ground reference for PHY TX1915PVDDRX-Positive 3.3V supply for PHY RX.P2016VDDPLL-Positive 3.3V supply for PHY PLL.2117PVSSPLLGround reference for PHY PLL-2218PVSSOSC-Ground reference foroscillator.2319-OSC1ANAOscillator input.0OSC22420Oscillator output.P2521VDDOSCPositive 3.3V supply for oscillator.-26220LEDB driver pin,(5)LEDB一27230LEDALEDA driver pin.(5)一2824PVDD1Positive 3.3V supplyLegend:I = Input, O = Output, P = Power, ANA = Analog Signal Input, ST = Schmitt Trigger1:NotePinshaveamaximumcurrentcapacityof8mA2: Pins haveamaximumcurrent capacityof4mA3:Pins are 5V tolerant.4:Pins have an internal weak pull-up to VDD.5:Pins havea maximum current capacity of 12 mA.PreliminaryDS39662C-page 42008 Microchip Technology Inc
ENC28J60 DS39662C-page 4 Preliminary © 2008 Microchip Technology Inc. FIGURE 1-2: TYPICAL ENC28J60-BASED INTERFACE TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description SPDIP, SOIC, SSOP QFN VCAP 1 25 P ó 2.5V output from internal regulator. A low Equivalent Series Resistance (ESR) capacitor, with a typical value of 10 mF and a minimum value of 1 mF to ground, must be placed on this pin. VSS 2 26 P ó Ground reference. CLKOUT 3 27 O ó Programmable clock output pin.(1) INT 4 28 O ó INT interrupt output pin.(2) NC 5 1 O ó Reserved function; always leave unconnected. SO 6 2 O ó Data out pin for SPI interface.(2) SI 7 3 I ST Data in pin for SPI interface.(3) SCK 8 4 I ST Clock in pin for SPI interface.(3) CS 9 5 I ST Chip select input pin for SPI interface.(3,4) RESET 10 6 I ST Active-low device Reset input.(3,4) VSSRX 11 7 P ó Ground reference for PHY RX. TPIN- 12 8 I ANA Differential signal input. TPIN+ 13 9 I ANA Differential signal input. RBIAS 14 10 I ANA Bias current pin for PHY. Must be tied to ground via a resistor (refer to Section 2.4 ìMagnetics, Termination and Other External Componentsî for details). VDDTX 15 11 P ó Positive supply for PHY TX. TPOUT- 16 12 O ó Differential signal output. TPOUT+ 17 13 O ó Differential signal output. VSSTX 18 14 P ó Ground reference for PHY TX. VDDRX 19 15 P ó Positive 3.3V supply for PHY RX. VDDPLL 20 16 P ó Positive 3.3V supply for PHY PLL. VSSPLL 21 17 P ó Ground reference for PHY PLL. VSSOSC 22 18 P ó Ground reference for oscillator. OSC1 23 19 I ANA Oscillator input. OSC2 24 20 O ó Oscillator output. VDDOSC 25 21 P ó Positive 3.3V supply for oscillator. LEDB 26 22 O ó LEDB driver pin.(5) LEDA 27 23 O ó LEDA driver pin.(5) VDD 28 24 P ó Positive 3.3V supply. Legend: I = Input, O = Output, P = Power, ANA = Analog Signal Input, ST = Schmitt Trigger Note 1: Pins have a maximum current capacity of 8 mA. 2: Pins have a maximum current capacity of 4 mA. 3: Pins are 5V tolerant. 4: Pins have an internal weak pull-up to VDD. 5: Pins have a maximum current capacity of 12 mA. TRANSFORMER MCU TX/RX Buffer MAC PHY LEDA LEDB SI SO SCK INT SDO SDI SCK INTX ENC28J60 TPIN+/- TPOUT+/- ETHERNET RJ45 I/O CS
ENC28J602.0EXTERNALCONNECTIONS2.2OscillatorStart-upTimerTheENC28J60contains anOscillatorStart-up Timer2.1Oscillator(OST)toensurethattheoscillatorand integratedPHYhave stabilized before use.The OST does not expireTheENC28J60isdesignedtooperateat25MHzwithuntil7500OsC1clockcycles (300μs)passaftera crystal connectedtotheOSC1andOSC2pins.ThePower-onResetorwake-upfromPower-DownmodeENC28J60 design requires the use of a parallel cutoccurs. During the delay,all Ethernet registers andcrystal.Use ofa series cut crystal may give a frequencybuffer memory may still be readand written to throughoutofthecrystalmanufacturerspecifications.AtypicaltheSPIbus.However,softwareshould notattempttooscillatorcircuit isshown inFigure2-1transmit any packets (set ECON1.TXRTS),enableTheENC28J60mayalsobedrivenbyanexternalclockreception ofpackets (setECON1.RXEN)oraccess anysource connected to the OsC1 pin as shown inMAC, MIl or PHY registers during this period.Figure 2-2.WhentheOSTexpires,theCLKRDYbit intheESTATregisterwill beset.TheapplicationsoftwareshouldpollFIGURE 2-1:CRYSTALOSCILLATORthis bit as necessary to determine when normal deviceOPERATIONoperation can begin.ENC28J60Note:AfteraPower-onReset,ortheENC28J60isremovedfromPower-Downmode,theOSC1-CLKRDYbitmustbepolledbeforetransmittingpackets,enablingpacketCTo Intemal Logic :reception or accessing any MAC,MIl or:1白XTALPHY registers.17:RF(2)-Rs(1)C2OSC2Note 1:A series resistor, Rs, may be required for ATstrip cut crystals2:The feedback resistor, RF,is typically in therange of2 to 10M2.EXTERNALCLOCKFIGURE 2-2:SOURCE(1)ENC28J603.3VClockfrom+oSC1External SystemOpen(2) OSC2Note1:Dutycyclerestrictionsmustbeobserved.2:Aresistorto ground may be usedto reducesystem noise.This may increase systemcurrent.Preliminary2008 Microchip Technology Inc.DS39662C-page 5
© 2008 Microchip Technology Inc. Preliminary DS39662C-page 5 ENC28J60 2.0 EXTERNAL CONNECTIONS 2.1 Oscillator The ENC28J60 is designed to operate at 25 MHz with a crystal connected to the OSC1 and OSC2 pins. The ENC28J60 design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturer specifications. A typical oscillator circuit is shown in Figure 2-1. The ENC28J60 may also be driven by an external clock source connected to the OSC1 pin as shown in Figure 2-2. FIGURE 2-1: CRYSTAL OSCILLATOR OPERATION FIGURE 2-2: EXTERNAL CLOCK SOURCE(1) 2.2 Oscillator Start-up Timer The ENC28J60 contains an Oscillator Start-up Timer (OST) to ensure that the oscillator and integrated PHY have stabilized before use. The OST does not expire until 7500 OSC1 clock cycles (300 μs) pass after Power-on Reset or wake-up from Power-Down mode occurs. During the delay, all Ethernet registers and buffer memory may still be read and written to through the SPI bus. However, software should not attempt to transmit any packets (set ECON1.TXRTS), enable reception of packets (set ECON1.RXEN) or access any MAC, MII or PHY registers during this period. When the OST expires, the CLKRDY bit in the ESTAT register will be set. The application software should poll this bit as necessary to determine when normal device operation can begin. C1 C2 XTAL OSC2 RS(1) OSC1 RF(2) To Internal Logic Note 1: A series resistor, RS, may be required for AT strip cut crystals. 2: The feedback resistor, RF, is typically in the range of 2 to 10 MΩ. ENC28J60 3.3V Clock from External System OSC1 Open OSC2 (2) Note 1: Duty cycle restrictions must be observed. 2: A resistor to ground may be used to reduce system noise. This may increase system current. ENC28J60 Note: After a Power-on Reset, or the ENC28J60 is removed from Power-Down mode, the CLKRDY bit must be polled before transmitting packets, enabling packet reception or accessing any MAC, MII or PHY registers
ENC28J602.3CLKOUTPinAdditionally,Power-Downmodemaybevalue).entered and the CLKOUT function will continuetoTheclock out pin isprovidedto the systemdesignerforoperate.When Power-Down mode is cancelled, theuseas thehostcontrollerclockorasaclocksourceforOST will bereset buttheCLKOUT function willotherdevicesin the system.TheCLKOUThasancontinue.When theCLKOUT function is disabledintemalprescalerwhichcandividetheoutputby1,2,(ECOCON=o),theCLKOUTpinisdrivenlow3,4or8.TheCLKOUTfunctionisenabledand theThe CLKOUT function is designed to ensure that mini-prescaler isselectedviatheECOCONregistermum timings are preserved when the CLKOUT pin(Register 2-1).function is enabled, disabled or the prescaler value isTocreateaclean clock signal,theCLKOUTpin isheldchanged.No high or low pulses will be outputted whichlowforaperiod whenpower is firstapplied.Aftertheexceed the frequency specified by the ECOCONPower-on Reset ends, the OST will begin counting.configuration.However,whenswitchingfrequencies,aWhen the OST expires, the CLKOUT pin willbegin out-delaybetweentwoandeightOSC1clockperiods willputting its default frequency of 6.25 MHz (main clockoccurwhere no clock pulses will be produced (seedivided by 4).At anyfuture time thatthe ENC28J60 isFigure 2-3). During this period, CLKOUT will be heldreset by softwareor the RESETpin, the CLKOUT func-low.tion will not be altered (ECOCONwill not changeFIGURE 2-3:CLKOUTTRANSITION1ECOCON80nsto320nsDelayChangedECOCON:CLOCKOUTPUTCONTROLREGISTERREGISTER 2-1:U-0U-0U-0U-0U-OR/W-1R/W-0R/W-0COCON2COCON1COCONObit 7bit oLegend:R= Readable bitW= Writable bitU=Unimplementedbit,readas01'= Bit is set-n = Value at POR'0'=Bit is clearedx = Bit is unknownbit 7-3Unimplemented:Readas'o'bit 2-0CocoN2:cocoNo:ClockOutputConfigurationbits11x=Reservedforfactorytest.Donotuse.Glitchpreventionnotassured.101=CLKOUT outputsmain clock divided by8 (3.125MHz)100=CLKOUToutputsmainclockdividedby4(6.25MHz)011=CLKOUToutputsmainclockdividedby3(8.333333MHz)010=CLKOUT outputsmain clock divided by2 (12.5MHz)001=CLKOUToutputsmainclockdividedby1(25MHz)000=CLKOUT isdisabled.Thepin is driven low.PreliminaryDS39662C-page 62008 Microchip Technology Inc
ENC28J60 DS39662C-page 6 Preliminary © 2008 Microchip Technology Inc. 2.3 CLKOUT Pin The clock out pin is provided to the system designer for use as the host controller clock or as a clock source for other devices in the system. The CLKOUT has an internal prescaler which can divide the output by 1, 2, 3, 4 or 8. The CLKOUT function is enabled and the prescaler is selected via the ECOCON register (Register 2-1). To create a clean clock signal, the CLKOUT pin is held low for a period when power is first applied. After the Power-on Reset ends, the OST will begin counting. When the OST expires, the CLKOUT pin will begin outputting its default frequency of 6.25 MHz (main clock divided by 4). At any future time that the ENC28J60 is reset by software or the RESET pin, the CLKOUT function will not be altered (ECOCON will not change value). Additionally, Power-Down mode may be entered and the CLKOUT function will continue to operate. When Power-Down mode is cancelled, the OST will be reset but the CLKOUT function will continue. When the CLKOUT function is disabled (ECOCON = 0), the CLKOUT pin is driven low. The CLKOUT function is designed to ensure that minimum timings are preserved when the CLKOUT pin function is enabled, disabled or the prescaler value is changed. No high or low pulses will be outputted which exceed the frequency specified by the ECOCON configuration. However, when switching frequencies, a delay between two and eight OSC1 clock periods will occur where no clock pulses will be produced (see Figure 2-3). During this period, CLKOUT will be held low. FIGURE 2-3: CLKOUT TRANSITION ECOCON Changed 80 ns to 320 ns Delay REGISTER 2-1: ECOCON: CLOCK OUTPUT CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 ó ó ó ó ó COCON2 COCON1 COCON0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ë0í -n = Value at POR ë1í = Bit is set ë0í = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ë0í bit 2-0 COCON2:COCON0: Clock Output Configuration bits 11x = Reserved for factory test. Do not use. Glitch prevention not assured. 101 = CLKOUT outputs main clock divided by 8 (3.125 MHz) 100 = CLKOUT outputs main clock divided by 4 (6.25 MHz) 011 = CLKOUT outputs main clock divided by 3 (8.333333 MHz) 010 = CLKOUT outputs main clock divided by 2 (12.5 MHz) 001 = CLKOUT outputs main clock divided by 1 (25 MHz) 000 = CLKOUT is disabled. The pin is driven low
ENC28J602.4Acommon-modechokeontheTPOUTinterface,placedMagnetics,TerminationandOtherbetweentheTPOUTpinsandtheEthernettransformerExternalComponents(not shown), is not recommended. If a common-modeTocomplete the Ethernet interface,the ENC28J60choke is usedto reduce EMI emissions,it should berequiresseveralstandardcomponentstobeinstalledplacedbetweentheEthernettransformerandpins1andexternally.Thesecomponents shouldbeconnectedas2of theRJ-45connector.Many Ethernettransformershown in Figure 2-4.modules includecommon-modechokes insidethesamedevicepackage.ThetransformersshouldhaveatleastThe internal analog circuitry in the PHY module requiresthe isolation rating specified in Table 16-5 to protectthatanexternal2.32k2,1%resistorbeattachedfromagainst static voltagesandmeetIEEE802.3isolationRBIAS to ground. The resistor influences the TPOUT+/-requirements(seeSection16.0"ElectricalCharacter-signal amplitude.Theresistorshould beplacedas closeistics"for specific transformer requirements).Bothaspossibletothechipwithnoimmediatelyadjacenttransmit and receive interfaces additionally require twosignaltracestopreventnoisecapacitivelycoupling intoresistors and a capacitor to properly terminate thethepin and affectingthe transmit behavior.Itistransmission line, minimizing signal reflections.recommended that theresistor bea surface mounttypeAllpowersupplypinsmustbeexternallyconnectedtoSome of the device's digital logicoperates at a nominathe same power source.Similarly,all ground refer-2.5V.An on-chip voltage regulator is incorporated toences must beexternallyconnectedto the samegeneratethis voltage.The only external componentground node.EachVDD andVsspinpair shouldhaverequiredisanexternalfiltercapacitor,connectedfroma0.1μFceramicbypasscapacitor(not shown in theVcAptoground.Thecapacitormusthavelowequiva-schematic)placedasclosetothepinsaspossible.lent series resistance (ESR), with a typical value of10μF,and a minimum value of 1μF.The internalSince relatively high currents are necessary to operateregulatoris notdesignedtodriveexternal loads.the twisted-pair interface, all wires should be kept asshort aspossible.Reasonablewirewidths shouldbeOn the TPIN+/TPIN-and TPOUT+/TPOUT-pinsused on power wires to reduce resistive loss. If the1:1centertapedpulsetransformers,ratedforEthernetdifferential data lines cannot be kept short, they shouldoperations,are required.When theEthernetmodule isberouted insuchawayastohavea1002characteristicenabled, current is continually sunk through bothimpedance.TPOUTpins.WhenthePHYis activelytransmitting,adifferential voltage is created on the Ethernet cable byvaryingtherelativecurrentsunkbyTPOUT+comparedto TPOUT-.FIGURE 2-4:ENC28J60ETHERNETTERMINATIONANDEXTERNALCONNECTIONS3.3VRJ-45ENC28J60MCULTPOUT+FerritecsVO-Bead(1,3)SCKSCK2?SISDO0.1 μF(3)≥49.90,1%SOSDI-13TPOUT-1:1CT-TPIN+4Level49.92, 1%Shift&I Logic(2) ;4531149.92,1%0.1 μFINT-INTO61:1 CTTPIN-RBIAS7VCAPLEDALEDBMMZ87503|7502(3）7502(3|750(3≥ 2.32 k2, 1%10 μFX1 nF, 2 kV(3)IN1:NoteFerrite Bead should be rated for at least 80 mARequired only if the microcontrolleris operating at 5V. See Section 2.5 "VO Levels" for more information.2:3:These components are installed for EMI reduction purposes.Preliminary2008 Microchip Technology inc.DS39662C-page 7
© 2008 Microchip Technology Inc. Preliminary DS39662C-page 7 ENC28J60 2.4 Magnetics, Termination and Other External Components To complete the Ethernet interface, the ENC28J60 requires several standard components to be installed externally. These components should be connected as shown in Figure 2-4. The internal analog circuitry in the PHY module requires that an external 2.32 kΩ, 1% resistor be attached from RBIAS to ground. The resistor influences the TPOUT+/- signal amplitude. The resistor should be placed as close as possible to the chip with no immediately adjacent signal traces to prevent noise capacitively coupling into the pin and affecting the transmit behavior. It is recommended that the resistor be a surface mount type. Some of the deviceís digital logic operates at a nominal 2.5V. An on-chip voltage regulator is incorporated to generate this voltage. The only external component required is an external filter capacitor, connected from VCAP to ground. The capacitor must have low equivalent series resistance (ESR), with a typical value of 10 μF, and a minimum value of 1 μF. The internal regulator is not designed to drive external loads. On the TPIN+/TPIN- and TPOUT+/TPOUT- pins, 1:1 center taped pulse transformers, rated for Ethernet operations, are required. When the Ethernet module is enabled, current is continually sunk through both TPOUT pins. When the PHY is actively transmitting, a differential voltage is created on the Ethernet cable by varying the relative current sunk by TPOUT+ compared to TPOUT-. A common-mode choke on the TPOUT interface, placed between the TPOUT pins and the Ethernet transformer (not shown), is not recommended. If a common-mode choke is used to reduce EMI emissions, it should be placed between the Ethernet transformer and pins 1 and 2 of the RJ-45 connector. Many Ethernet transformer modules include common-mode chokes inside the same device package. The transformers should have at least the isolation rating specified in Table 16-5 to protect against static voltages and meet IEEE 802.3 isolation requirements (see Section 16.0 ìElectrical Characteristicsî for specific transformer requirements). Both transmit and receive interfaces additionally require two resistors and a capacitor to properly terminate the transmission line, minimizing signal reflections. All power supply pins must be externally connected to the same power source. Similarly, all ground references must be externally connected to the same ground node. Each VDD and VSS pin pair should have a 0.1 μF ceramic bypass capacitor (not shown in the schematic) placed as close to the pins as possible. Since relatively high currents are necessary to operate the twisted-pair interface, all wires should be kept as short as possible. Reasonable wire widths should be used on power wires to reduce resistive loss. If the differential data lines cannot be kept short, they should be routed in such a way as to have a 100Ω characteristic impedance. FIGURE 2-4: ENC28J60 ETHERNET TERMINATION AND EXTERNAL CONNECTIONS I/O SCK SDO SDI INT0 MCU Level Shift Logic(2) CS SCK SI SO INT ENC28J60 VCAP LEDA LEDB RBIAS TPOUT+ TPOUTTPIN+ TPIN- 10 μF Note 1: Ferrite Bead should be rated for at least 80 mA. 2: Required only if the microcontroller is operating at 5V. See Section 2.5 ìI/O Levelsî for more information. 3: These components are installed for EMI reduction purposes. Ferrite Bead(1,3) 3.3V 2.32 kΩ, 1% 1 2 3 4 5 6 7 8 RJ-45 1:1 CT 1:1 CT 1 nF, 2 kV(3) 75Ω(3) 75Ω(3) 75Ω(3) 75Ω(3) 49.9Ω, 1% 49.9Ω, 1% 49.9Ω, 1% 49.9Ω, 1% 0.1 μF(3) 0.1 μF 1
ENC28J602.5/OLevels2.6LED ConfigurationTheENC28J60isa3.3Vpart:howeveritwasTheLEDAand LEDB pins support automatic polaritydesignedtobeeasilyintegratedinto5Vsystems.Thedetection on Reset.TheLEDscan be connected suchSPI CS, SCK and SI inputs, as well as the RESET pin,that the pinmust source current to tun the LED on,orare all 5V tolerant. On the other hand, if the hostalternately connected such that the pin must sink cur-controlleris operated at5V,it quite likelywill not berentto turn the LED on. Upon system Reset, thewithin specifications when its SPI and interrupt inputsENC28J60willdetecthowtheLED isconnectedandare driven bythe 3.3VCMOS outputs onthebegin drivingthe LEDtothedefault stateconfiguredbyENC28J60.Aunidirectional leveltranslatorwouldbethePHLCON register.If the LED polarity is changedwhile the ENC28J60 is operating,the new polarity willnecessary.notbe detected until the next system Reset occurs.Aneconomical74HCT08(quadANDgate),74ACT125(quad 3-state buffer) or many other 5V CMOS chipsLEDB is unique in that the connection of the LED iswithTTLlevelinputbuffersmaybeusedtoprovidetheautomaticallyread onResetanddetermineshowtainitialize thePHCON1.PDPXMD bit.If the pin sourcesnecessary level shifting.The use of 3-state bufferspermits easyintegration intosystemswhich sharethecurrent to illuminate the LED,the bit is cleared onSPI bus with other devices. Figure 2-5 and Figure 2-6ResetandthePHYdefaultstohalf-duplexoperation.Ifshowexampletranslationschemes.the pin sinks currentto illuminate the LED, the bit is setonResetandthePHYdefaultstofull-duplexoperationFIGURE 2-5:LEVELSHIFTINGUSINGFigure2-7showsthetwoavailableoptions.If noLEDisattachedtotheLEDBpin,thePDPXMDbit will resetANDGATESto an indeterminate value.MCUENC28J60FIGURE 2-7:LEDBPOLARITYANDRESETCONFIGURATIONcs+VOOPTIONSVSCKSCKSISO+Full-Duplex Operation:Q+3.3VPDPXMD =1sIsoVCLKOUTOSC1LEDBINTINTO斤Half-Duplex Operation:PDPXMD=0FIGURE2-6:LEVELSHIFTINGUSINGLEDB13-STATEBUFFERSMCUENC28J60csVO-SCKSCKSIsOTheLEDscan alsobeconfigured separatelyto controltheiroperating polarity (on oroff when active),blinkrateSOSIand blink stretch interval.The options are controlled bytheLACFG3:LACFGO andLBCFG3:LBCFG0bitsCLKOUTOSC1TypicalvaluesforblinkstretcharelistedinTable2-1.INTINTOTABLE 2-1:LEDBLINKSTRETCHLENGTHStretch LengthTypical Stretch (ms)40TNSTRCH (normal)70TMSTRCH (medium)140TLSTRCH (long)PreliminaryDS39662C-page 8?2008MicrochipTechnology Inc
ENC28J60 DS39662C-page 8 Preliminary © 2008 Microchip Technology Inc. 2.5 I/O Levels The ENC28J60 is a 3.3V part; however, it was designed to be easily integrated into 5V systems. The SPI CS, SCK and SI inputs, as well as the RESET pin, are all 5V tolerant. On the other hand, if the host controller is operated at 5V, it quite likely will not be within specifications when its SPI and interrupt inputs are driven by the 3.3V CMOS outputs on the ENC28J60. A unidirectional level translator would be necessary. An economical 74HCT08 (quad AND gate), 74ACT125 (quad 3-state buffer) or many other 5V CMOS chips with TTL level input buffers may be used to provide the necessary level shifting. The use of 3-state buffers permits easy integration into systems which share the SPI bus with other devices. Figure 2-5 and Figure 2-6 show example translation schemes. FIGURE 2-5: LEVEL SHIFTING USING AND GATES FIGURE 2-6: LEVEL SHIFTING USING 3-STATE BUFFERS 2.6 LED Configuration The LEDA and LEDB pins support automatic polarity detection on Reset. The LEDs can be connected such that the pin must source current to turn the LED on, or alternately connected such that the pin must sink current to turn the LED on. Upon system Reset, the ENC28J60 will detect how the LED is connected and begin driving the LED to the default state configured by the PHLCON register. If the LED polarity is changed while the ENC28J60 is operating, the new polarity will not be detected until the next system Reset occurs. LEDB is unique in that the connection of the LED is automatically read on Reset and determines how to initialize the PHCON1.PDPXMD bit. If the pin sources current to illuminate the LED, the bit is cleared on Reset and the PHY defaults to half-duplex operation. If the pin sinks current to illuminate the LED, the bit is set on Reset and the PHY defaults to full-duplex operation. Figure 2-7 shows the two available options. If no LED is attached to the LEDB pin, the PDPXMD bit will reset to an indeterminate value. FIGURE 2-7: LEDB POLARITY AND RESET CONFIGURATION OPTIONS The LEDs can also be configured separately to control their operating polarity (on or off when active), blink rate and blink stretch interval. The options are controlled by the LACFG3:LACFG0 and LBCFG3:LBCFG0 bits. Typical values for blink stretch are listed in Table 2-1. TABLE 2-1: LED BLINK STRETCH LENGTH I/O SCK SO SI INT0 MCU CS SCK SI SO INT ENC28J60 OSC1 CLKOUT I/O SCK SO SI INT0 MCU CS SCK SI SO INT ENC28J60 OSC1 CLKOUT Stretch Length Typical Stretch (ms) TNSTRCH (normal) 40 TMSTRCH (medium) 70 TLSTRCH (long) 140 LEDB Full-Duplex Operation: +3.3V PDPXMD = 1 LEDB Half-Duplex Operation: PDPXMD = 0