Abstract Abstract A 12-bit 320-MSample/s current-steering D/A converter with the supply voltage of 1.8-v is presented.In order to achieve high linearity and spurious free dynamic range(SFDR),a large degree of segmentation has been used, with the seven most significant bits(MSBs)being implemented as equally weighted current sources.As for each extra bit of accuracy,the gate-area of the current source transistors in the cell matrix must increase by a factor of 4 so that the transistor matching is within the desired accuracy.In addition,the area overhead due to the interconnect lines and the additional circuitry roughly doubles.As consequence,the cell matrix has dimensions of several hundred microns,and it becomes increasingly difficult to minimize the impact of the systematic mismatch sources on the DAC accuracy due to process, temperature,and electric gradients.To solve this problem,this design used the CSA approach,in which the current sources alone are laid out in an array separated from the rest of the circuitry which is then laid out in a bit slice fashion.This approach has the advantage that the current-source transistors can be divided into multiple strips placed throughout the CSA to cancel gradient effects.In addition if each individual strips is equivalent to 1LSBs unit scaling between the unary MSBs and the binary LSBs is possible,thus eliminating scaling errors.However,if gradient cancellation is implemented for the linear bits,access to the multiple transistor strips becomes more difficult and the interconnect between the CSA and the bit slice increasingly dramatically in complexity as the amount of segmentation increases. Key words:D/A converter,segment,thermometer-code,binary code,current source array(CSA),matchingAbstract 2 Abstract A 12-bit 320-MSample/s current-steering D/A converter with the supply voltage of 1.8-v is presented. In order to achieve high linearity and spurious free dynamic range (SFDR), a large degree of segmentation has been used, with the seven most significant bits (MSBs) being implemented as equally weighted current sources. As for each extra bit of accuracy, the gate-area of the current source transistors in the cell matrix must increase by a factor of 4 so that the transistor matching is within the desired accuracy. In addition, the area overhead due to the interconnect lines and the additional circuitry roughly doubles. As consequence, the cell matrix has dimensions of several hundred microns, and it becomes increasingly difficult to minimize the impact of the systematic mismatch sources on the DAC accuracy due to process, temperature, and electric gradients. To solve this problem, this design used the CSA approach, in which the current sources alone are laid out in an array separated from the rest of the circuitry which is then laid out in a bit slice fashion. This approach has the advantage that the current-source transistors can be divided into multiple strips placed throughout the CSA to cancel gradient effects. In addition if each individual strips is equivalent to 1LSBs unit scaling between the unary MSBs and the binary LSBs is possible, thus eliminating scaling errors. However, if gradient cancellation is implemented for the linear bits, access to the multiple transistor strips becomes more difficult and the interconnect between the CSA and the bit slice increasingly dramatically in complexity as the amount of segmentation increases. Key words: D/A converter, segment, thermometer-code, binary code, current source array (CSA), matching