2015 Fifth International Conference on Communication Systems and Network Technologies DESIGN AND TESTING OF COMBINATIONAL LOGIC CIRCUITS USING BUILT IN SELF TEST SCHEME FOR FPGAS Nagaraj S Vannal Saroja V Siddamal Shruti V Bidaralli Mahalaxmi S Bhille Asst.Prof,Dept.of IT, Associate.Prof.Dept.of Department of ECE. Asst.Prof,Dept.of ISE BVBCET,Hubli, ECE,BVBCET,Hubli, BVBCET,Hubli, BVBCET,Hubli. Karnataka,India Karnataka,India Karnataka,India Karnataka.India nagaraj vannal@bvb.edu sarojavs@bvb.edu shruthibidaralli@gmail.com mahalaxmi.bhille@bvb.edu Abstract-In Very Large Scale Integration (VLSD,while understand why,consider the example of a 1 GHz manufacturing IC,Test time and cost plays a very significant microprocessor on a chip with 800 pins.For reliable stuck- role.If faulty components find during IC manufacture then cost fault and limited transition-delay fault testing,we should increases.So it is essential to minimize test time and cost.In this conduct the test at the rated clock speed.This forces us to use paper Built In Self Test (BIST)architecture is designed for the Advantest Model T6682 1 GHz ATE,which can sample testing combinational logic circuits and fault models like stuck at one and stuck at zero are tested,simulated and validated using circuit outputs at this rate.The tester costs 800 pins x $6,000 Spartan 6 FPGA and Xilinx ISE 14.2 tool.BIST architecture per pin =4,800,000,but there is no chip area cost due to with fault and without fault in circuit under test is compared for testing,because we do not use on-chip BIST hardware. the parameters such as area,memory,delays time and device Therefore,there is a huge initial capital cost for the ATE utilization. but there is no recurring chip area cost on each chip for test hardware.If,instead,we provide BIST hardware,then the Keywords-BIST;LFSR;MISR;CUT;S-A-1;S-A-0; need for a very high-speed ATE is eliminated,except to test the wires from the circuit pins to the Input MUX,and from the L INTRODUCTION circuit outputs to the output pins.The number of tests for that With the ever-increasing complexity and density of present is very short,say perhaps 7 or 8 patterns and measurements per pin,and the cost of this can be safely ignored in this day integrated circuits,the cost of testing has become a analysis.Therefore,with BIST doing all stuck-fault and significant part of the overall product.Thereby,Built-In Self- Test (BIST)has been proposed as a powerful design for transition delay fault testing.we need a I GHz signal oscillator to clock the chip,and we need the ATE only to provide DC testability technique for addressing the highly complex testing command signals to tell the microprocessor to perform BIST. BIST design includes on-chip/board circuitry to provide test Finally,we need an ATE to read out the success or failure DC patterns and to analyze output responses.It can perform the signal for BIST from a circuit pin.In this case,we can use an test internal to the chip so that the need for complex external inexpensive,20 MHz ATE that costs roughly S391 per pin,so testing equipment is greatly reduced.Using BIST many of the traditional testing problems (low accessibility of internal our cost is 800 pins x $391 per pin =$312,800,a savings of $4,487,200.This example is hardly far fetched.On-chip clock nodes that increases the test complexity)can be overcome [1]. Another interesting feature of BIST strategies is that it rates are expected to rise above 1 GHz,and at present,no ATE exists to test a circuit above 1 GHz [2]. allows rapid testing of the circuit.The test is performed at the nominal operation frequency without resorting to an extemal high speed tester that represents an expensive Automatic Test II.BIST ARCHITECTURE Equipment (ATE)and which additionally does not always Built in self test is a design for testability (DFT)technique have a timing accuracy comparable to the IC internal speed on in which testing is carried out using built in hardware features. the boards. Advantage of this methodology is that the test patterns are not BIST reduces testing costs.In order to understand why, applied by external Automatic Test Equipments (ATEs)but consider the example of a 1 GHz microprocessor on a chip generated by inbuilt testing circuit.It saves the memory with 800 pins.For reliable stuck-fault and limited transition- requirement during test.A typical BIST architecture consists delay fault testing,we should conduct the test at the rated of a test pattern generator (TPG),usually implemented as a clock speed.This forces us to use the Advantest Model T6682 linear feedback shift register (LFSR),a test response analyzer 1 GHZ ATE,which can sample circuit outputs at this rate.The (TRA),implemented as a multiple input shift register(MISR). Tester costs 800 pins x S6,000 per pin =4,800,000,but there and a BIST control unit(BCU),all implemented on the chip as is no chip area cost due to testing,because we do not use on- shown in Figure 1[2].This approach allows applying at-speed chip BIST hardware.BIST reduces testing costs.In order to IEEE 978-1-4799-1797-6W15$31.0002015IEEE 903 Φcomputer DOI10.1109/CSNT.2015.151 societyDESIGN AND TESTING OF COMBINATIONAL LOGIC CIRCUITS USING BUILT IN SELF TEST SCHEME FOR FPGAs Nagaraj S Vannal Asst. Prof, Dept. of IT, BVBCET, Hubli, Karnataka, India nagaraj_vannal@bvb.edu Saroja V Siddamal Associate. Prof, Dept. of ECE, BVBCET, Hubli, Karnataka, India sarojavs@bvb.edu Shruti V Bidaralli Department of ECE, BVBCET, Hubli, Karnataka, India shruthibidaralli@gmail.com Mahalaxmi S Bhille Asst. Prof, Dept. of ISE BVBCET, Hubli, Karnataka, India mahalaxmi.bhille@bvb.edu Abstract— In Very Large Scale Integration (VLSI), while manufacturing IC, Test time and cost plays a very significant role. If faulty components find during IC manufacture then cost increases. So it is essential to minimize test time and cost. In this paper Built In Self Test (BIST) architecture is designed for testing combinational logic circuits and fault models like stuck at one and stuck at zero are tested, simulated and validated using Spartan 6 FPGA and Xilinx ISE 14.2 tool. BIST architecture with fault and without fault in circuit under test is compared for the parameters such as area, memory, delays time and device utilization. Keywords— BIST; LFSR; MISR; CUT; S-A-1; S-A-0; I. INTRODUCTION With the ever-increasing complexity and density of present day integrated circuits, the cost of testing has become a significant part of the overall product. Thereby, Built-In Self￾Test (BIST) has been proposed as a powerful design for testability technique for addressing the highly complex testing. BIST design includes on-chip/board circuitry to provide test patterns and to analyze output responses. It can perform the test internal to the chip so that the need for complex external testing equipment is greatly reduced. Using BIST many of the traditional testing problems (low accessibility of internal nodes that increases the test complexity) can be overcome [1]. Another interesting feature of BIST strategies is that it allows rapid testing of the circuit. The test is performed at the nominal operation frequency without resorting to an external high speed tester that represents an expensive Automatic Test Equipment (ATE) and which additionally does not always have a timing accuracy comparable to the IC internal speed on the boards. BIST reduces testing costs. In order to understand why, consider the example of a 1 GHz microprocessor on a chip with 800 pins. For reliable stuck-fault and limited transition￾delay fault testing, we should conduct the test at the rated clock speed. This forces us to use the Advantest Model T6682 1 GHz ATE, which can sample circuit outputs at this rate. The Tester costs 800 pins × $6,000 per pin = $ 4,800,000, but there is no chip area cost due to testing, because we do not use on￾chip BIST hardware. BIST reduces testing costs. In order to understand why, consider the example of a 1 GHz microprocessor on a chip with 800 pins. For reliable stuck￾fault and limited transition-delay fault testing, we should conduct the test at the rated clock speed. This forces us to use the Advantest Model T6682 1 GHz ATE, which can sample circuit outputs at this rate. The tester costs 800 pins × $6,000 per pin = $ 4,800,000, but there is no chip area cost due to testing, because we do not use on-chip BIST hardware. Therefore, there is a huge initial capital cost for the ATE, but there is no recurring chip area cost on each chip for test hardware. If, instead, we provide BIST hardware, then the need for a very high-speed ATE is eliminated, except to test the wires from the circuit pins to the Input MUX, and from the circuit outputs to the output pins. The number of tests for that is very short, say perhaps 7 or 8 patterns and measurements per pin, and the cost of this can be safely ignored in this analysis. Therefore, with BIST doing all stuck-fault and transition delay fault testing, we need a 1 GHz signal oscillator to clock the chip, and we need the ATE only to provide DC command signals to tell the microprocessor to perform BIST. Finally, we need an ATE to read out the success or failure DC signal for BIST from a circuit pin. In this case, we can use an inexpensive, 20 MHz ATE that costs roughly $391 per pin, so our cost is 800 pins × $391 per pin = $312,800, a savings of $4,487,200. This example is hardly far fetched. On-chip clock rates are expected to rise above 1 GHz, and at present, no ATE exists to test a circuit above 1 GHz [2]. II. BIST ARCHITECTURE Built in self test is a design for testability (DFT) technique in which testing is carried out using built in hardware features. Advantage of this methodology is that the test patterns are not applied by external Automatic Test Equipments (ATEs) but generated by inbuilt testing circuit. It saves the memory requirement during test. A typical BIST architecture consists of a test pattern generator (TPG), usually implemented as a linear feedback shift register (LFSR), a test response analyzer (TRA), implemented as a multiple input shift register (MISR), and a BIST control unit (BCU), all implemented on the chip as shown in Figure 1[2]. This approach allows applying at-speed 2015 Fifth International Conference on Communication Systems and Network Technologies 978-1-4799-1797-6/15 $31.00 © 2015 IEEE DOI 10.1109/CSNT.2015.151 903