2015 Fifth International Conference on Communication Systems and Network Technologies DESIGN AND TESTING OF COMBINATIONAL LOGIC CIRCUITS USING BUILT IN SELF TEST SCHEME FOR FPGAS Nagaraj S Vannal Saroja V Siddamal Shruti V Bidaralli Mahalaxmi S Bhille Asst.Prof,Dept.of IT, Associate.Prof.Dept.of Department of ECE. Asst.Prof,Dept.of ISE BVBCET,Hubli, ECE,BVBCET,Hubli, BVBCET,Hubli, BVBCET,Hubli. Karnataka,India Karnataka,India Karnataka,India Karnataka.India nagaraj vannal@bvb.edu sarojavs@bvb.edu shruthibidaralli@gmail.com mahalaxmi.bhille@bvb.edu Abstract-In Very Large Scale Integration (VLSD,while understand why,consider the example of a 1 GHz manufacturing IC,Test time and cost plays a very significant microprocessor on a chip with 800 pins.For reliable stuck- role.If faulty components find during IC manufacture then cost fault and limited transition-delay fault testing,we should increases.So it is essential to minimize test time and cost.In this conduct the test at the rated clock speed.This forces us to use paper Built In Self Test (BIST)architecture is designed for the Advantest Model T6682 1 GHz ATE,which can sample testing combinational logic circuits and fault models like stuck at one and stuck at zero are tested,simulated and validated using circuit outputs at this rate.The tester costs 800 pins x $6,000 Spartan 6 FPGA and Xilinx ISE 14.2 tool.BIST architecture per pin =4,800,000,but there is no chip area cost due to with fault and without fault in circuit under test is compared for testing,because we do not use on-chip BIST hardware. the parameters such as area,memory,delays time and device Therefore,there is a huge initial capital cost for the ATE utilization. but there is no recurring chip area cost on each chip for test hardware.If,instead,we provide BIST hardware,then the Keywords-BIST;LFSR;MISR;CUT;S-A-1;S-A-0; need for a very high-speed ATE is eliminated,except to test the wires from the circuit pins to the Input MUX,and from the L INTRODUCTION circuit outputs to the output pins.The number of tests for that With the ever-increasing complexity and density of present is very short,say perhaps 7 or 8 patterns and measurements per pin,and the cost of this can be safely ignored in this day integrated circuits,the cost of testing has become a analysis.Therefore,with BIST doing all stuck-fault and significant part of the overall product.Thereby,Built-In Self- Test (BIST)has been proposed as a powerful design for transition delay fault testing.we need a I GHz signal oscillator to clock the chip,and we need the ATE only to provide DC testability technique for addressing the highly complex testing command signals to tell the microprocessor to perform BIST. BIST design includes on-chip/board circuitry to provide test Finally,we need an ATE to read out the success or failure DC patterns and to analyze output responses.It can perform the signal for BIST from a circuit pin.In this case,we can use an test internal to the chip so that the need for complex external inexpensive,20 MHz ATE that costs roughly S391 per pin,so testing equipment is greatly reduced.Using BIST many of the traditional testing problems (low accessibility of internal our cost is 800 pins x $391 per pin =$312,800,a savings of $4,487,200.This example is hardly far fetched.On-chip clock nodes that increases the test complexity)can be overcome [1]. Another interesting feature of BIST strategies is that it rates are expected to rise above 1 GHz,and at present,no ATE exists to test a circuit above 1 GHz [2]. allows rapid testing of the circuit.The test is performed at the nominal operation frequency without resorting to an extemal high speed tester that represents an expensive Automatic Test II.BIST ARCHITECTURE Equipment (ATE)and which additionally does not always Built in self test is a design for testability (DFT)technique have a timing accuracy comparable to the IC internal speed on in which testing is carried out using built in hardware features. the boards. Advantage of this methodology is that the test patterns are not BIST reduces testing costs.In order to understand why, applied by external Automatic Test Equipments (ATEs)but consider the example of a 1 GHz microprocessor on a chip generated by inbuilt testing circuit.It saves the memory with 800 pins.For reliable stuck-fault and limited transition- requirement during test.A typical BIST architecture consists delay fault testing,we should conduct the test at the rated of a test pattern generator (TPG),usually implemented as a clock speed.This forces us to use the Advantest Model T6682 linear feedback shift register (LFSR),a test response analyzer 1 GHZ ATE,which can sample circuit outputs at this rate.The (TRA),implemented as a multiple input shift register(MISR). Tester costs 800 pins x S6,000 per pin =4,800,000,but there and a BIST control unit(BCU),all implemented on the chip as is no chip area cost due to testing,because we do not use on- shown in Figure 1[2].This approach allows applying at-speed chip BIST hardware.BIST reduces testing costs.In order to IEEE 978-1-4799-1797-6W15$31.0002015IEEE 903 Φcomputer DOI10.1109/CSNT.2015.151 society
DESIGN AND TESTING OF COMBINATIONAL LOGIC CIRCUITS USING BUILT IN SELF TEST SCHEME FOR FPGAs Nagaraj S Vannal Asst. Prof, Dept. of IT, BVBCET, Hubli, Karnataka, India nagaraj_vannal@bvb.edu Saroja V Siddamal Associate. Prof, Dept. of ECE, BVBCET, Hubli, Karnataka, India sarojavs@bvb.edu Shruti V Bidaralli Department of ECE, BVBCET, Hubli, Karnataka, India shruthibidaralli@gmail.com Mahalaxmi S Bhille Asst. Prof, Dept. of ISE BVBCET, Hubli, Karnataka, India mahalaxmi.bhille@bvb.edu Abstract— In Very Large Scale Integration (VLSI), while manufacturing IC, Test time and cost plays a very significant role. If faulty components find during IC manufacture then cost increases. So it is essential to minimize test time and cost. In this paper Built In Self Test (BIST) architecture is designed for testing combinational logic circuits and fault models like stuck at one and stuck at zero are tested, simulated and validated using Spartan 6 FPGA and Xilinx ISE 14.2 tool. BIST architecture with fault and without fault in circuit under test is compared for the parameters such as area, memory, delays time and device utilization. Keywords— BIST; LFSR; MISR; CUT; S-A-1; S-A-0; I. INTRODUCTION With the ever-increasing complexity and density of present day integrated circuits, the cost of testing has become a significant part of the overall product. Thereby, Built-In SelfTest (BIST) has been proposed as a powerful design for testability technique for addressing the highly complex testing. BIST design includes on-chip/board circuitry to provide test patterns and to analyze output responses. It can perform the test internal to the chip so that the need for complex external testing equipment is greatly reduced. Using BIST many of the traditional testing problems (low accessibility of internal nodes that increases the test complexity) can be overcome [1]. Another interesting feature of BIST strategies is that it allows rapid testing of the circuit. The test is performed at the nominal operation frequency without resorting to an external high speed tester that represents an expensive Automatic Test Equipment (ATE) and which additionally does not always have a timing accuracy comparable to the IC internal speed on the boards. BIST reduces testing costs. In order to understand why, consider the example of a 1 GHz microprocessor on a chip with 800 pins. For reliable stuck-fault and limited transitiondelay fault testing, we should conduct the test at the rated clock speed. This forces us to use the Advantest Model T6682 1 GHz ATE, which can sample circuit outputs at this rate. The Tester costs 800 pins × $6,000 per pin = $ 4,800,000, but there is no chip area cost due to testing, because we do not use onchip BIST hardware. BIST reduces testing costs. In order to understand why, consider the example of a 1 GHz microprocessor on a chip with 800 pins. For reliable stuckfault and limited transition-delay fault testing, we should conduct the test at the rated clock speed. This forces us to use the Advantest Model T6682 1 GHz ATE, which can sample circuit outputs at this rate. The tester costs 800 pins × $6,000 per pin = $ 4,800,000, but there is no chip area cost due to testing, because we do not use on-chip BIST hardware. Therefore, there is a huge initial capital cost for the ATE, but there is no recurring chip area cost on each chip for test hardware. If, instead, we provide BIST hardware, then the need for a very high-speed ATE is eliminated, except to test the wires from the circuit pins to the Input MUX, and from the circuit outputs to the output pins. The number of tests for that is very short, say perhaps 7 or 8 patterns and measurements per pin, and the cost of this can be safely ignored in this analysis. Therefore, with BIST doing all stuck-fault and transition delay fault testing, we need a 1 GHz signal oscillator to clock the chip, and we need the ATE only to provide DC command signals to tell the microprocessor to perform BIST. Finally, we need an ATE to read out the success or failure DC signal for BIST from a circuit pin. In this case, we can use an inexpensive, 20 MHz ATE that costs roughly $391 per pin, so our cost is 800 pins × $391 per pin = $312,800, a savings of $4,487,200. This example is hardly far fetched. On-chip clock rates are expected to rise above 1 GHz, and at present, no ATE exists to test a circuit above 1 GHz [2]. II. BIST ARCHITECTURE Built in self test is a design for testability (DFT) technique in which testing is carried out using built in hardware features. Advantage of this methodology is that the test patterns are not applied by external Automatic Test Equipments (ATEs) but generated by inbuilt testing circuit. It saves the memory requirement during test. A typical BIST architecture consists of a test pattern generator (TPG), usually implemented as a linear feedback shift register (LFSR), a test response analyzer (TRA), implemented as a multiple input shift register (MISR), and a BIST control unit (BCU), all implemented on the chip as shown in Figure 1[2]. This approach allows applying at-speed 2015 Fifth International Conference on Communication Systems and Network Technologies 978-1-4799-1797-6/15 $31.00 © 2015 IEEE DOI 10.1109/CSNT.2015.151 903
tests and eliminates the need for an external tester.The BIST architecture components are given below [131. Test Pattern Generator (TPG) LFSR Circuit under Test CLK BIST (CUT) Controller RST Combinational circuit Figure 2:Circuit diagram of 3 bit LFSR B.Circuit Under Test(CUT) Test Response Analyzer (TRA) T- Test Result/ In this paper circuit under test is a combinational circuit MISR Signature show in the figure 3.The different types of test carried are with respect to Stuck-at fault.It means that the fault is modeled by assigning a fixed(0 or 1)value to a single line in Figure 1:Basic block diagram of a BIST the circuit (in this case 1s NAND gate).A single line is an Test pattern Generator(TPG):Test pattern generator (TPG) input or an output of a logic gate or a flip-flop.Stuck-at fault generates the test patterns for CUT.It is a dedicated circuit can be derived into two parts one is single stuck-at fault or a microprocessor.The patterns may be generated in another one is multiple stuck-at faults,a stuck-at fault is pseudorandom or deterministically [8]. assumed to affect only the interconnection between gates. Circuit under Test(CUT):Circuit under Test(CUT)is the However,multiple fault diagnosis becomes increasing portion of the circuit tested in BIST mode.It can be difficulty and time-consuming as the size of integrated circuit sequential,combinational or a memory. increases.Many of methods have been introduced for Test Response Analyzer(TRA):Test Response Analyzer diagnosing and deducing fault locations multiple faults in (TRA)analyses the value sequence on primary output and combinational circuit such as effect-cause analysis,guided- compares it with the expected output BIST controller unit.It probing,analysis by forward propagation and backward controls the test execution;it manages the Test pattern implication using randomly generated input-pairs[8],analysis and diagnosis using both electron beam and LSI tester. generator (TPG),Circuit under Test (CUT),Test Response Analyzer (TRA)and reconfigures the CUT.It is activated We have proposed methods to deduce suspected faults by algorithmically-generated sensitizing input-pairs without by the normal/test signal and generates a go/no go. probing internal lines.To reduce the number of suspected Multiple Input Signature Register(MISR):Multiple Input faults,single and multiple fault simulation with diagnostic Signature Register(MISR)is designed for signature tests that lead to fault-free responses are used to identify non analysis which is a technique for data compression.MIPS are frequently implemented in BIST designs,in which existent faults.To avoid missing actual faults in a fault circuit output responses are compressed by MISR.MISR the proposed method uses the result of multiple fault simulation to diagnose multiple stuck-at faults.On the efficiently map different input streams to different signatures with every small probability of alias. assumption that all suspected faults are equally likely in the faulty circuit,multiple faults simulations are performed. IIL.PROPOSED DESIGN METHODOLOGY A.Linear Feedback Shift Register Struck-at-1 LFSR is a shift register whose input bit is a linear function of its previous state [9].The most commonly used linear Struck-at-0 function of single bits is XOR.Thus,an LFSR is most often a shift register whose input bit is driven by the exclusive-or (XOR)of some bits of the overall shift register value.Pseudo random number sequence generator [8]is generated in HDL according to the following circuit based on the concept of shift register as shown in Figure 2[3][4].Combinational circuit in CUT requires only 3 inputs.3-bit LFSR is sufficient for the implementation of TPG [5]. Figure 3:Flow chart of CUT 904
tests and eliminates the need for an external tester. The BIST architecture components are given below [13]. Figure 1: Basic block diagram of a BIST • Test pattern Generator (TPG): Test pattern generator (TPG) generates the test patterns for CUT. It is a dedicated circuit or a microprocessor. The patterns may be generated in pseudorandom or deterministically [8]. • Circuit under Test (CUT): Circuit under Test (CUT) is the portion of the circuit tested in BIST mode. It can be sequential, combinational or a memory. • Test Response Analyzer (TRA): Test Response Analyzer (TRA) analyses the value sequence on primary output and compares it with the expected output BIST controller unit. It controls the test execution; it manages the Test pattern generator (TPG), Circuit under Test (CUT), Test Response Analyzer (TRA) and reconfigures the CUT. It is activated by the normal/test signal and generates a go/no go. • Multiple Input Signature Register (MISR): Multiple Input Signature Register(MISR) is designed for signature analysis which is a technique for data compression. MIPS are frequently implemented in BIST designs, in which output responses are compressed by MISR. MISR efficiently map different input streams to different signatures with every small probability of alias. III. PROPOSED DESIGN METHODOLOGY A. Linear Feedback Shift Register LFSR is a shift register whose input bit is a linear function of its previous state [9]. The most commonly used linear function of single bits is XOR. Thus, an LFSR is most often a shift register whose input bit is driven by the exclusive-or (XOR) of some bits of the overall shift register value. Pseudo random number sequence generator [8] is generated in HDL according to the following circuit based on the concept of shift register as shown in Figure 2[3][4]. Combinational circuit in CUT requires only 3 inputs. 3-bit LFSR is sufficient for the implementation of TPG [5]. Figure 2: Circuit diagram of 3 bit LFSR B. Circuit Under Test(CUT) In this paper circuit under test is a combinational circuit show in the figure 3. The different types of test carried are with respect to Stuck-at fault. It means that the fault is modeled by assigning a fixed (0 or 1) value to a single line in the circuit (in this case 1st NAND gate). A single line is an input or an output of a logic gate or a flip-flop. Stuck-at fault can be derived into two parts one is single stuck-at fault another one is multiple stuck-at faults, a stuck-at fault is assumed to affect only the interconnection between gates. However, multiple fault diagnosis becomes increasing difficulty and time-consuming as the size of integrated circuit increases. Many of methods have been introduced for diagnosing and deducing fault locations multiple faults in combinational circuit such as effect-cause analysis, guidedprobing, analysis by forward propagation and backward implication using randomly generated input-pairs[8], analysis and diagnosis using both electron beam and LSI tester. We have proposed methods to deduce suspected faults by algorithmically-generated sensitizing input-pairs without probing internal lines. To reduce the number of suspected faults, single and multiple fault simulation with diagnostic tests that lead to fault-free responses are used to identify non existent faults. To avoid missing actual faults in a fault circuit the proposed method uses the result of multiple fault simulation to diagnose multiple stuck-at faults. On the assumption that all suspected faults are equally likely in the faulty circuit, multiple faults simulations are performed. Figure 3: Flow chart of CUT 904
C.Multiple Input Signature-analysis Register (MISR) We can combine the PRBS generator of Figure 2 together A Multiple Input Signature-analysis Register (MISR)is with the signature register of Figure 3 to form the simple BIST one which can be used to reduce the amount of hardware structure for testing combinational circuit shown in Figure 3 required to compress a multiple bit stream.The MISR LFSR generates a maximal-length(22-1 =7 cycles)PRBS provides an alternative to using multiple Linear Feedback MISR computes the signature of the CUT with s-a-1.LFSR is Shift Registers(LFSRs)in parallel and separately comparing initialized to '101'(a 1,b=1.c=1)and MISR is initialized the error polynomials.Test patterns for BIST can be generated to '101'.The schematic in Figure 5 shows how the TPG and at-speed by an LFSR with only a clock input.Then the outputs TRA are used for testing CUT to s-a-1&s-a-0 fault.Table I of the CUT (Circuit under Test)must be compared to the shows how the bit sequences are calculated in the good circuit. known good response which is termed as the golden signature. The signature is formed in MISR and compared with circuit Signature analysis is the most popular compaction technique under test.We can observe the change in bits for MISR used today.Multiple input signature register (MISR)is the output, because of s-a-1 and s-a-0 faults present in the solution that compact all outputs into a single LFSR.It works combinational circuit because LFSR is linear and obeys superposition principle.All responses are superimposed into one LFSR.The final TEST PATTERN GENERATOR (LFSR) TEST RESPONSE ANALYSER OMUISR) remainder is the XOR sum of remainders of polynomial divisions of each Primary Output by the characteristic polynomial.Its output develops a signature based on the effect of all the bits fed into it.If any bit is wrong,the signature will be different from the expected value and a fault will have been detected[6]. A Single-Input Signature Register (SISR)has been designed for this project.There are several ways to connect the inputs of LFSRs to form an SISR.Since the XOR operation is linear and associative,(A Xor B)Xor C=A Xor GOOD AND BADOUPUI (B Xor C),as long as the result of the additions are the same 9+1010U00310601000]0101110 then the different representations are equivalent.If we have an n-bit long SISR we can accommodate up to n inputs to form 0101010006 the signature.If we use m n inputs we do not need the extra Circmit Uader Test (comb circuit) 010001001o110011101 XOR gates in the last n-m positions of the SISR.SISR reduce the amount of hardware required to compress a multiple bit stream.LFSR and/or SISR circuit is implemented using a memory already existing in a circuit to be tested.If we apply a binary input sequence to LFSR,the shift register will Figure 5:Circuit diagram of proposed BIST Architecture [11] perform data compaction (or compression)on the input The MISR output with good circuit response as sequence [11] 101010001000100010101110.If s-a-1 fault is present at the input of second NAND gate the MISR output response At the end of the input sequence the shift-register contents, Q0,Q1,and Q2,will form a pattern that we call a signature.If changes to 101010001000000000000000 and because of s-a-0 fault presence the MISR output response changes to the input sequence and the serial-input signature register 101010001000100110011101 (SISR)are long enough,it is unlikely (though possible)that two different input sequences will produce the same signature. TABLE L BIT SEQUENCES OF PROPOSED BIST ARCHITECTURE If the input sequence comes from logic that we wish to test,a INPUTS OUTPUT fault in the logic will cause the input sequence to change.This With S causes the signature to change from a known good value and Without With S-A-1 b A-0 we shall then know that the circuit under test is bad.This fault fault technique,called signature analysis,was developed by Fault Hewlett-Packard to test equipment in the field in the late 1 1 1 1 1970s.The simplest form of this technique is based on a single input LFSR [11]. 0 1 1 1 00 1 0 (1) O 0 0 0 0 D000 D202 00 0 0 1 DATA IN 000 0 0 1 MISR o/p without 101 010 001 000 100 010 101 110 fault MISR o/p CLK with s-a-l 101 010 001 000 i000 000 000 000 tault RST MISR o/p with sa-0 101 010 001 000 100 110 011 101 fault Figure 4:Circuit diagram of 3 bit Single Input Signature Register(SISR) 905
C. Multiple Input Signature-analysis Register (MISR) A Multiple Input Signature-analysis Register (MISR) is one which can be used to reduce the amount of hardware required to compress a multiple bit stream. The MISR provides an alternative to using multiple Linear Feedback Shift Registers (LFSRs) in parallel and separately comparing the error polynomials. Test patterns for BIST can be generated at-speed by an LFSR with only a clock input. Then the outputs of the CUT (Circuit under Test) must be compared to the known good response which is termed as the golden signature. Signature analysis is the most popular compaction technique used today. Multiple input signature register (MISR) is the solution that compact all outputs into a single LFSR. It works because LFSR is linear and obeys superposition principle. All responses are superimposed into one LFSR. The final remainder is the XOR sum of remainders of polynomial divisions of each Primary Output by the characteristic polynomial. Its output develops a signature based on the effect of all the bits fed into it. If any bit is wrong, the signature will be different from the expected value and a fault will have been detected[6]. A Single-Input Signature Register (SISR) has been designed for this project. There are several ways to connect the inputs of LFSRs to form an SISR. Since the XOR operation is linear and associative, (A Xor B) Xor C = A Xor (B Xor C), as long as the result of the additions are the same then the different representations are equivalent. If we have an n -bit long SISR we can accommodate up to n inputs to form the signature. If we use m < n inputs we do not need the extra XOR gates in the last n – m positions of the SISR. SISR reduce the amount of hardware required to compress a multiple bit stream. LFSR and/or SISR circuit is implemented using a memory already existing in a circuit to be tested. If we apply a binary input sequence to LFSR, the shift register will perform data compaction (or compression) on the input sequence [11]. At the end of the input sequence the shift-register contents, Q0, Q1, and Q2, will form a pattern that we call a signature. If the input sequence and the serial-input signature register (SISR) are long enough, it is unlikely (though possible) that two different input sequences will produce the same signature. If the input sequence comes from logic that we wish to test, a fault in the logic will cause the input sequence to change. This causes the signature to change from a known good value and we shall then know that the circuit under test is bad. This technique, called signature analysis, was developed by Hewlett-Packard to test equipment in the field in the late 1970s. The simplest form of this technique is based on a single input LFSR [11]. Figure 4: Circuit diagram of 3 bit Single Input Signature Register (SISR) We can combine the PRBS generator of Figure 2 together with the signature register of Figure 3 to form the simple BIST structure for testing combinational circuit shown in Figure 3. LFSR generates a maximal-length (23 – 1 = 7 cycles) PRBS. MISR computes the signature of the CUT with s-a-1. LFSR is initialized to '101' (a = 1, b = 1, c = 1) and MISR is initialized to '101'. The schematic in Figure 5 shows how the TPG and TRA are used for testing CUT to s-a-1& s-a-0 fault. Table I shows how the bit sequences are calculated in the good circuit. The signature is formed in MISR and compared with circuit under test. We can observe the change in bits for MISR output, because of s-a-1 and s-a-0 faults present in the combinational circuit. Figure 5: Circuit diagram of proposed BIST Architecture [11] The MISR output with good circuit response as 101010001000100010101110. If s-a-1 fault is present at the input of second NAND gate the MISR output response changes to 101010001000000000000000 and because of s-a-0 fault presence the MISR output response changes to 101010001000100110011101. TABLE I: BIT SEQUENCES OF PROPOSED BIST ARCHITECTURE 905
IV.RESULTS AND DISCUSSION output signal for the top module.The combinational circuit In this paper BIST architecture has been designed for under test is having input from LFSR and output is connected combinational circuit using Spartan 6 FPGA and Xilinx ISE to MISR. 14.2 tool. Output sequences-111110101011110101010100001001 First the 3-bit LFSR simulation result using XILINX 14.2 Figure 6(b)shows the BIST design output for CUT with tool is observed by applying input signals Clock and Reset.23 fault.Clock and reset are the 2 inputs and data out is an random pattern sequences are generated at the output signal. output signal for the top module.The combinational circuit Then MISR simulation result using XILINX 14.2 tool is under test is having stuck at fault because of that the change in evaluated by inputting signals Clock,Reset and data in the output is (output signal from CUT for BIST design).23random pattern sequences are generated at the output signal. Output sequences-11111010101010l010101011111110 Figure 6(a)shows the BIST design output for CUT without fault.Clock and reset are the 2 inputs and data out is an 288.000n3 Name Value 200ns 220ns Le rstni data_outi2:0] 100 111 110X101X011X110X101X010■ 100X001X011X1 Le clkl_period 10000P 1000ps X1288.000ns Figure 6(a):Simulation of BIST Architecture without Fault 568.000n9 Name Value 300 ns 1320ns 340s 360ns 380n 400ns 1 0 data_out1[2:0] 011 0X110●X4101 010101010○101 011○X0 111 ●X110 clikd_period 10000P 10000p5 Change of ouput sequence bits because of struck at faults X1:368.000ns Figure 6(b):Simulation of BIST Architecture with Fault 906
IV. RESULTS AND DISCUSSION In this paper BIST architecture has been designed for combinational circuit using Spartan 6 FPGA and Xilinx ISE 14.2 tool. First the 3-bit LFSR simulation result using XILINX 14.2 tool is observed by applying input signals Clock and Reset. 23 random pattern sequences are generated at the output signal. Then MISR simulation result using XILINX 14.2 tool is evaluated by inputting signals Clock, Reset and data_in (output signal from CUT for BIST design). 23 random pattern sequences are generated at the output signal. Figure 6 (a) shows the BIST design output for CUT without fault. Clock and reset are the 2 inputs and data_out is an output signal for the top module. The combinational circuit under test is having input from LFSR and output is connected to MISR. Output sequences –111 110 101 011 110 101 010 100 001 001 Figure 6 (b) shows the BIST design output for CUT with fault. Clock and reset are the 2 inputs and data_out is an output signal for the top module. The combinational circuit under test is having stuck at fault because of that the change in the output is Output sequences –111 110 101 010 101 010 101 011 111 110 Figure 6(a): Simulation of BIST Architecture without Fault Figure 6(b): Simulation of BIST Architecture with Fault 906
TABLE II:PERFORMANCE COMPARISON CONCLUSION In this paper BIST architecture has been designed for BIST for BIST for CUT CUT combinational circuit using Spartan 6 FPGA and Xilinx ISE CUT Parameters CUT with with without 14.2 tool.Memory usage,Delay time reductions because of without Fault fault Fault fault BIST design into CUT with fault and without fault are 5%, 8%.46%and 19%respectively.Memory usage with BIST Clock consumes lesser area when we compare with CUT period 1000ps 1000ps 1000ps 1000ps with/without fault.Delay time without BIST takes longer Memory time to complete execution of required result.By seeing 187616KB 188116KB 187232KB 187992KB Usage these little variations in parameters justifies the BIST technique for combinational circuit will not affect the area Levels of overhead,memory issues and power consumption. Logic 2 2 References [1]Nagaraj S Vannal,Mahalaxmi S Bhille and Shanmuk S Vannal, Real time 4.00s 4.00s 3.00s 5.00s "Design and Implementation of Built in Self-Test mechanism to minimize the test cost test repair cycle",Intemational Journal of Systems Algorithms&Applications,Volume 3,Issue ICRASE13. CPU time 4.54s 4.04s 3.55s 5.16s May2013,1SSN0 nline:2277-2677,pp.156-159. [2]Essentials of electronic testing for digital,memory and Mixed signal Time for VLSI circuits by Michael L.Bushnell Rutgers University, Vishwan simulation 10ns 10ns 10ns 10ns D.Agrawal,Bell Labs,Lucent Technologies. [3 Panda Amit K,Rajput P,Shukla B,"Design of Multi Bit LFSR Delay 2.690s 7.266ns 3.536s 5.385ns PNRG and Performance comparison on FPGA using VHDL" Intemational Journal of Advances in Engineering Technology (IJAET),Mar 2012,Vol.3,Issue 1,pp.566-571. Power 0.029w 0.029w [4] Sewak K.Rajput P.Panda Amit K."FPGA Implementation of 16 bit 0.029w 0.029w BBS and LFSR PN Sequence Generator:A Comparative Study",In Proce.of the IEEE Student Conference on Electrical,Electronics and Computer Sciences 2012,1-2 Mar 2012,NIT Bhopal,India 9 ) R.David,"Signature Analysis of Multi-Output Circuits,"in Proc.of the International Fault-Tolerant Computing Symp.,June 1984,pp. 366-371. [6] Application-Specific Integrated Circuits by Michael John Sebastian Smith Copyright 1997 by Addison Wesley Longman,Inc 6 ▣BIST FOR CUT [] Essays,UK.(November 2013).Built In Self Test Computer Science Essay.Retrieved from http://www.ukessays.com/essays/computer- WITH FAULT science/built-in-self-test-computer-science-essay.php?cref=1 [8] "Comparison Between Random and Pseudo-Random Generation for 3 ■BIST FOR CUT (2000)"by Patrick Girard,Christian Landrault,Serge Pravossoudovitch,Arnaud Virazel 2 WITHOUT FAULT [9] http://en.wikipedia.org/wiki/Linear feedback shift register [10]Implementation And Testing Of Adders Using BIST Published By Deepthi Veeramachaneni Https://Www.Scribd.Com/Doc/118684054/IMPLEMENTATION MEMORY USAGEIIN PERCENTAGE) AND-TESTING-OF-ADDERS-USING-BIST [11]http://iroi.seuedu.cn/books/asics/Book2/CH14/CH14.7.htm Figure 7(a):Graphical esentation of Memory usage of BIST Design [12]"A New Method for Diagnosing Multiple Stuck-at-Faults using Multiple and Single Fault Simulations"By An-jen Cheng Electrical 50 and Computer Engineering, Auburn University 45 http://www.eng.auburn.edu/-agrawvd/COURSE/E7250 05/REPORT 40 S_TERM/Cheng_Multiple_revised.doc [13]http://www.engineersgarage.com/contribution/power-optimization-of- 3 BIST FOR CUT Ifsr?page=2 WITH FAULT [14]http://www.slideshare.net/ijsmeteditorial/implementation-of-low- power-test-pattem-generatorusing-lfsr 25 20 ■BIST FOR CUT 15 WITHOUT FAULT 10 5 0 DELAY TIME[IN PERCENTAGE) Figure 7(b):Graphical representation of Delay Time of BIST Design 907
TABLE II: PERFORMANCE COMPARISON Figure 7(a): Graphical representation of Memory usage of BIST Design Figure 7(b): Graphical representation of Delay Time of BIST Design CONCLUSION In this paper BIST architecture has been designed for combinational circuit using Spartan 6 FPGA and Xilinx ISE 14.2 tool. Memory usage, Delay time reductions because of BIST design into CUT with fault and without fault are 5%, 8%, 46% and 19% respectively. Memory usage with BIST consumes lesser area when we compare with CUT with/without fault. Delay time without BIST takes longer time to complete execution of required result. By seeing these little variations in parameters justifies the BIST technique for combinational circuit will not affect the area overhead, memory issues and power consumption. REFERENCES [1] Nagaraj S Vannal, Mahalaxmi S Bhille and Shanmuk S Vannal, “Design and Implementation of Built in Self -Test mechanism to minimize the test cost & test repair cycle”, International Journal of Systems Algorithms & Applications, Volume 3, Issue ICRASE13, May 2013, ISSN Online: 2277-2677, pp. 156-159. [2] Essentials of electronic testing for digital, memory and Mixed signal VLSI circuits by Michael L. Bushnell Rutgers University, Vishwani D. Agrawal, Bell Labs, Lucent Technologies. [3] Panda Amit K, Rajput P, Shukla B, “Design of Multi Bit LFSR PNRG and Performance comparison on FPGA using VHDL”, International Journal of Advances in Engineering & Technology (IJAET), Mar 2012, Vol. 3, Issue 1, pp. 566-571. [4] Sewak K, Rajput P, Panda Amit K, “FPGA Implementation of 16 bit BBS and LFSR PN Sequence Generator: A Comparative Study”, In Proce. of the IEEE Student Conference on Electrical, Electronics and Computer Sciences 2012, 1-2 Mar 2012, NIT Bhopal, India [5] R. David, “Signature Analysis of Multi-Output Circuits,” in Proc. of the International Fault-Tolerant Computing Symp., June 1984, pp. 366–371. [6] Application-Specific Integrated Circuits by Michael John Sebastian Smith Copyright © 1997 by Addison Wesley Longman, Inc [7] Essays, UK. (November 2013). Built In Self Test Computer Science Essay. Retrieved from http://www.ukessays.com/essays/computerscience/built-in-self-test-computer-science-essay.php?cref=1 [8] “Comparison Between Random and Pseudo-Random Generation for (2000)” by Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel [9] http://en.wikipedia.org/wiki/Linear_feedback_shift_register [10] Implementation And Testing Of Adders Using BIST Published By Deepthi Veeramachaneni Https://Www.Scribd.Com/Doc/118684054/IMPLEMENTATIONAND-TESTING-OF-ADDERS-USING-BIST [11] http://iroi.seu.edu.cn/books/asics/Book2/CH14/CH14.7.htm [12] “A New Method for Diagnosing Multiple Stuck-at-Faults using Multiple and Single Fault Simulations” By An-jen Cheng Electrical and Computer Engineering, Auburn University, http://www.eng.auburn.edu/~agrawvd/COURSE/E7250_05/REPORT S_TERM/Cheng_Multiple_revised.doc [13] http://www.engineersgarage.com/contribution/power-optimization-oflfsr?page=2 [14] http://www.slideshare.net/ijsrneteditorial/implementation-of-lowpower-test-pattern-generatorusing-lfsr Parameters BIST for CUT with Fault CUT with fault BIST for CUT without Fault CUT without fault Clock period 1000 ps 1000 ps 1000 ps 1000 ps Memory Usage 187616 KB 188116KB 187232 KB 187992KB Levels of Logic 1 2 2 3 Real time 4.00 s 4.00 s 3.00 s 5.00 s CPU time 4.54 s 4.04 s 3.55 s 5.16 s Time for simulation 10 ns 10ns 10 ns 10ns Delay 2.690 ns 7.266 ns 3.536 ns 5.385 ns Power 0.029 w 0.029 w 0.029 w 0.029 w 907