IEEE AUTOTESTCON 2008 Salt Lake City,UT,8-11 September 2008 IC design-for-test and testability features Ron Press Mentor Graphics Corporation Abstract-IC test is at a mature state where automated tools are ICs.Though,IC complexity steadily increased to the point used for DFT feature insertion and pattern generation.This paper where functional test became too impractical for most summarizes the most common digital IC design-for-test (DFT) devices.Once device integration started to include tens of techniques in use today.Most of the focus is on testing and thousands of gates,it became a challenge to know the validating the correct operation of ICs after fabrication.However. operation of the device well enough to create a functional many of the IC DFT features can also be re-used in higher level test and in the field.In addition,some of the concepts in the well known test.Even if the functional test could be manually created,it strategies used for IC testing may be also effective for higher level would be very difficult to grade the effectiveness of the test of assembly test.Some of the topics presented on include scan, and determine any logic in the device that wasn't tested. automatic test pattern generation (ATPG).boundary scan,built-in Structural test approaches were developed because self-test (BIST),memory BIST and repair,secure IC test, creating very thorough functional tests became unrealistic for diagnostics,and test challenges. many ICs.Today,it is not uncommon for us to see ICs with tens or hundreds of millions of gates within them.What was Keywords scan.ATPG.built-in self-test,BIST,IC test.LPCT. needed was a method to break down the enormous structured test. complexity of an IC into simpler functions.In particular, sequential states drive most of the complexity within an IC. I.IC TEST QUALITY REQUIREMENTS For instance,it could require thousands or tens of thousands of clock cycles to propagate one value at a primary input High quality test for ICs is extremely important for many through the IC sequential logic before a single output can be products and can have a dramatic impact on system and predicted. assembly costs.A device that goes into a two dollar musical Scan technology replaces all the sequential elements(flip greeting card may be acceptable not to test at all prior to flops or latches)with a special device called a scan cell.Scan assembly.However,a device that is assembled into a ten cells operate the same as the standard sequential device in thousand dollar circuit board has a significant impact if it is functional operation.When a scan enable (SE)signal is defective.The cost of test and cost impact of a defect driven high then the scan cells are placed into a scan test increases dramatically with each progressive level of mode and scan cells are configured into long shift registers. assembly.As a result,the IC test has become well referred to as scan chains.An example is shown in the figure understood and standardized approaches are capable of below.When SE is asserted,all sequential gates can be detecting most defects.Test quality of ICs is at the state that initialized by shifting in known values from a tester into some companies are confident that out of every one million scan_in(SI).As a result,it is very easy to set up a desired parts shipped less than 50 defective parts will escape their test initial state.Then SE can be set to zero and the circuit will be methods.Defects per million(DPM)is the common term for in a normal mode of operation.Thus,if the clock is pulsed. how many defective parts escape test out of every million all the internal values from the combinational logic will be parts shipped. captured into the sequential logic as in a normal functional Parts that are known to be well tested make the task of clock cycle.Next.SE is asserted again and all the captured higher level assembly testing much easier.Known good ICs values can be shifted out for tester verification. assembled on a board only need to be tested to verify that board level manufacturing defects didn't occur.So,instead of having to test the function of the board,many companies can just check the board interconnects and chip 10. IC manufacturers understand the impact of shipping S defective parts and the direct correlation to their profitability. an Out SE This is especially true if the IC is assembled into a mission- critical product;a defect could result in loss of life and ruin the manufacturer's reputation and business. Figure 1.Scan structure provides controllability and observability to each internal sequential element. II.SCAN TEST AND ATPG Scan test converts the functional device with typically Conceptually,it might seem logical to simply test an IC by only a few hundred primary input and output pins into an checking that it functionally operates how it was designed to extremely testable circuit.In scan mode,the IC appears as work.Functional testing was the common approach for early just combinational logic between hundreds of thousands and 978-1-4244-2226-5/08/S25.00©20081EEE
IC design-for-test and testability features Ron Press Mentor Graphics Corporation Abstract – IC test is at a mature state where automated tools are used for DFT feature insertion and pattern generation. This paper summarizes the most common digital IC design-for-test (DFT) techniques in use today. Most of the focus is on testing and validating the correct operation of ICs after fabrication. However, many of the IC DFT features can also be re-used in higher level test and in the field. In addition, some of the concepts in the well known strategies used for IC testing may be also effective for higher level of assembly test. Some of the topics presented on include scan, automatic test pattern generation (ATPG), boundary scan, built-in self-test (BIST), memory BIST and repair, secure IC test, diagnostics, and test challenges. Keywords – scan, ATPG, built-in self-test, BIST, IC test, LPCT, structured test. I. IC TEST QUALITY REQUIREMENTS High quality test for ICs is extremely important for many products and can have a dramatic impact on system and assembly costs. A device that goes into a two dollar musical greeting card may be acceptable not to test at all prior to assembly. However, a device that is assembled into a ten thousand dollar circuit board has a significant impact if it is defective. The cost of test and cost impact of a defect increases dramatically with each progressive level of assembly. As a result, the IC test has become well understood and standardized approaches are capable of detecting most defects. Test quality of ICs is at the state that some companies are confident that out of every one million parts shipped less than 50 defective parts will escape their test methods. Defects per million (DPM) is the common term for how many defective parts escape test out of every million parts shipped. Parts that are known to be well tested make the task of higher level assembly testing much easier. Known good ICs assembled on a board only need to be tested to verify that board level manufacturing defects didn’t occur. So, instead of having to test the function of the board, many companies can just check the board interconnects and chip IO. IC manufacturers understand the impact of shipping defective parts and the direct correlation to their profitability. This is especially true if the IC is assembled into a missioncritical product; a defect could result in loss of life and ruin the manufacturer’s reputation and business. II. SCAN TEST AND ATPG Conceptually, it might seem logical to simply test an IC by checking that it functionally operates how it was designed to work. Functional testing was the common approach for early ICs. Though, IC complexity steadily increased to the point where functional test became too impractical for most devices. Once device integration started to include tens of thousands of gates, it became a challenge to know the operation of the device well enough to create a functional test. Even if the functional test could be manually created, it would be very difficult to grade the effectiveness of the test and determine any logic in the device that wasn’t tested. Structural test approaches were developed because creating very thorough functional tests became unrealistic for many ICs. Today, it is not uncommon for us to see ICs with tens or hundreds of millions of gates within them. What was needed was a method to break down the enormous complexity of an IC into simpler functions. In particular, sequential states drive most of the complexity within an IC. For instance, it could require thousands or tens of thousands of clock cycles to propagate one value at a primary input through the IC sequential logic before a single output can be predicted. Scan technology replaces all the sequential elements (flip flops or latches) with a special device called a scan cell. Scan cells operate the same as the standard sequential device in functional operation. When a scan_enable (SE) signal is driven high then the scan cells are placed into a scan test mode and scan cells are configured into long shift registers, referred to as scan chains. An example is shown in the figure below. When SE is asserted, all sequential gates can be initialized by shifting in known values from a tester into scan_in (SI). As a result, it is very easy to set up a desired initial state. Then SE can be set to zero and the circuit will be in a normal mode of operation. Thus, if the clock is pulsed, all the internal values from the combinational logic will be captured into the sequential logic as in a normal functional clock cycle. Next, SE is asserted again and all the captured values can be shifted out for tester verification. Figure 1. Scan structure provides controllability and observability to each internal sequential element. Scan test converts the functional device with typically only a few hundred primary input and output pins into an extremely testable circuit. In scan mode, the IC appears as just combinational logic between hundreds of thousands and IEEE AUTOTESTCON 2008 Salt Lake City, UT, 8-11 September 2008 978-1-4244-2226-5/08/$25.00 ©2008 IEEE
often millions of scan cell control and observation points. The scan cells essentially partition the complex sequential nature of a device into small combinational logic blocks Logic BIST Controller between controllable and observable scan cells.Testing is Clock Control Shift Pattern greatly simplified.The structure and individual gates are Logic Counter Counter targeted and verified rather than try to understand and confirm the functional operation of the device.If the pieces PRPG work then the functional assembly will work.The test Core MISR problem is simplified enough through scan that automated Scan Chains test pattern generation (ATPG)tools can automatically produce extremely thorough test patterns just based on the design netlist.Specific circuit functional knowledge is not necessary. Scan Chains Ⅲ. BUILT-IN SELF-TEST Test Points and X-bounding Figure 2.Logic BIST block diagram There is so much controllability and observability with scan that even random values loaded into the scan chains can IV. MEMORY BIST provide relatively effective tests.Embedding a built-in self- test (BIST)function on top of the scan structure can enable The scan and logic BIST techniques mentioned above the entire test system to be located within the IC.Some provide high quality test for random logic.Often one half or additional logic is used to produce the following functions: more of the silicon on an IC is used for memory arrays.Scan Pseudo-random pattern generation(PRPG):linear test is able to automatically test through the memory and feedback shift register (LFSR)that produces target faults at the memory IO.However,the memory cell predictable and repeatable but random looking array(silicon that stores the data)isn't thoroughly tested with values.This is the data that gets loaded into the scan.Instead,specific pattern sequences are used to test the scan chains. memories to ensure that common defects within the cell array Multiple-input shift register (MISR):similar to are not present.These test algorithms are very regular and an LFSR but it XORs in all the scan chain easy to generate using embedded test logic.Therefore,it is outputs and compacts them into a signature. common practice to design memory BIST in the silicon. After all patterns are applied and scan results During the test mode,the memory BIST controller will take compacted in the MISR,the final signature is control of the memory inputs and perform writes and reads verified against a known good signature. using predefined algorithms.One memory BIST controller is BIST controller:includes counters to change able to test many memories in parallel. from shift mode to functional mode within each pattern and a pattern counter to know when testing is complete. Test logic:prevents unknown states from propagating into the MISR and corrupting the signature.Often additional test logic is used to RAN make logic that is hard to test randomly more testable. Since the logic BIST is fully embedded,it can be applied at any level of configuration.The only requirement is that a simple MISR signature is verified.However,even the signature can be verified within the IC and a pass/fail signal can be used to check the results. Figure 3.Memory BIST block diagram Since the cell arrays take up so much silicon and are very dense,the probability of a defect can be relatively high Fortunately,the regular structure of cell arrays is easy to repair using spare memory logic.Thus,defective devices can be recognized by the memory BIST and a utility called built- in self analysis(BISA)will determine if the failure(s)are repairable.Then a repair operation occurs within the silicon
often millions of scan cell control and observation points. The scan cells essentially partition the complex sequential nature of a device into small combinational logic blocks between controllable and observable scan cells. Testing is greatly simplified. The structure and individual gates are targeted and verified rather than try to understand and confirm the functional operation of the device. If the pieces work then the functional assembly will work. The test problem is simplified enough through scan that automated test pattern generation (ATPG) tools can automatically produce extremely thorough test patterns just based on the design netlist. Specific circuit functional knowledge is not necessary. III. BUILT-IN SELF-TEST There is so much controllability and observability with scan that even random values loaded into the scan chains can provide relatively effective tests. Embedding a built-in selftest (BIST) function on top of the scan structure can enable the entire test system to be located within the IC. Some additional logic is used to produce the following functions: • Pseudo-random pattern generation (PRPG): linear feedback shift register (LFSR) that produces predictable and repeatable but random looking values. This is the data that gets loaded into the scan chains. • Multiple-input shift register (MISR): similar to an LFSR but it XORs in all the scan chain outputs and compacts them into a signature. After all patterns are applied and scan results compacted in the MISR, the final signature is verified against a known good signature. • BIST controller: includes counters to change from shift mode to functional mode within each pattern and a pattern counter to know when testing is complete. • Test logic: prevents unknown states from propagating into the MISR and corrupting the signature. Often additional test logic is used to make logic that is hard to test randomly more testable. Since the logic BIST is fully embedded, it can be applied at any level of configuration. The only requirement is that a simple MISR signature is verified. However, even the signature can be verified within the IC and a pass/fail signal can be used to check the results. Figure 2. Logic BIST block diagram IV. MEMORY BIST The scan and logic BIST techniques mentioned above provide high quality test for random logic. Often one half or more of the silicon on an IC is used for memory arrays. Scan test is able to automatically test through the memory and target faults at the memory IO. However, the memory cell array (silicon that stores the data) isn’t thoroughly tested with scan. Instead, specific pattern sequences are used to test the memories to ensure that common defects within the cell array are not present. These test algorithms are very regular and easy to generate using embedded test logic. Therefore, it is common practice to design memory BIST in the silicon. During the test mode, the memory BIST controller will take control of the memory inputs and perform writes and reads using predefined algorithms. One memory BIST controller is able to test many memories in parallel. Figure 3. Memory BIST block diagram Since the cell arrays take up so much silicon and are very dense, the probability of a defect can be relatively high. Fortunately, the regular structure of cell arrays is easy to repair using spare memory logic. Thus, defective devices can be recognized by the memory BIST and a utility called builtin self analysis (BISA) will determine if the failure(s) are repairable. Then a repair operation occurs within the silicon Logic BIST Controller Core PRPG Test Points and X-bounding Scan Chains Scan Chains Clock Control Logic MISR Shift Counter Pattern Counter
by redundancy substitution such that the memory becomes compactor operational. decompressor design core x+8++1 V.TESTING FOR SUBTLE DEFECTS scan chains Scan and memory BIST provide an excellent level of test and often can easily provide high levels of defect detection with standard pattern types.Fabrication technologies used in recent years enable more integration of gates within each IC and faster functional frequencies.Unfortunately,one side effect was that the defect distributions shifted.Traditional scan testing continues to detect most defects but the population of more subtle defects started raising the DPM levels.In particular,timing-related defects are not detected mask register with standard scan and were often responsible for one half or more of the defective parts that were escaping test. Trying to operate testers at IC frequencies could be very Figure 4.Embedded deterministic test enables high quality targeted challenging,especially for IC frequencies greater than 200 pattern but with 100x fewer tester cycles per pattem. MHz.A well adopted solution is to use the existing functional internal clock generation logic or PLLs embedded VI BOUNDARY SCAN AND HIGHER LEVEL TEST within the IC [1].Scan patterns can be loaded as normal using an external tester clock.The scan patterns include data Some IC test structures are primarily used for higher level that places the PLL clock generation logic in a mode such testing.Boundary scan technology was developed to provide that several at-speed clock pulsed can be produced internally a simple method of testing for board-level (or MCM) to capture results using functional clocks.As a result,timing manufacturing defects.A test structure is added to the IC IO defects can be detected but the resolution of the timing is pins with a controller.A four to five pin test access port internally generated.The accuracy of the clocking and test is (TAP)controls a state machine that operates the boundary independent of the tester capabilities since the internal PLL is scan test modes.Boundary scan test is similar to scan,except used [2].These at-speed scan patterns are popular today and the control and observability are via boundary scan cells several other newer types of scan patterns are gaining in placed at each of the device's functional IO.The boundary usage. scan test process consists of loading values into the boundary The growth in scan patterns has a big impact on test time scan registers,applying them to the device outputs and onto and cost.Embedded scan compression techniques were the board interconnects,capturing the responses at other developed to enable all the additional scan pattern types to be device pin inputs,and shifting out for verification.Thus,the applied but without any additional tester time or cost [3]. board level manufacturing defects can be checked without They embed additional logic between the devices IO and scan having to understand the Ic designs or propagate signals chains.This logic acts as a transform function to take tester through them.In addition,the interface to thoroughly test the data and expand it to many short internal scan chains that board is through a simple four to five pin standard port. ensure detection of targeted faults.Scan cell values that do Connecting to the various device IO signals is not necessary not contribute to detection for that pattern are loaded with Boundary scan is common on many commercial products and random values from the embedded logic instead of storing standardized as IEEE standard 1149.1. data on the tester.As a result,the tester loads and verifies values similar to normal scan test patterns but the load and unload time is fifty to one hundred times faster.The highest Chip 2 level of test quality is possible because the patterns are deterministic,specifically targeting faults,and due to the compression all the pattern types can be applied without cost TD implications.The need to apply more test patterns has driven TCK Circuit Prior to Cireui Prior to the usage of embedded compression to be more popular than Boundary Scar Boundary Scan Inse rtion traditional scan. Figure 5.Board with two devices containing boundary scan
by redundancy substitution such that the memory becomes operational. V. TESTING FOR SUBTLE DEFECTS Scan and memory BIST provide an excellent level of test and often can easily provide high levels of defect detection with standard pattern types. Fabrication technologies used in recent years enable more integration of gates within each IC and faster functional frequencies. Unfortunately, one side effect was that the defect distributions shifted. Traditional scan testing continues to detect most defects but the population of more subtle defects started raising the DPM levels. In particular, timing-related defects are not detected with standard scan and were often responsible for one half or more of the defective parts that were escaping test. Trying to operate testers at IC frequencies could be very challenging, especially for IC frequencies greater than 200 MHz. A well adopted solution is to use the existing functional internal clock generation logic or PLLs embedded within the IC [1]. Scan patterns can be loaded as normal using an external tester clock. The scan patterns include data that places the PLL clock generation logic in a mode such that several at-speed clock pulsed can be produced internally to capture results using functional clocks. As a result, timing defects can be detected but the resolution of the timing is internally generated. The accuracy of the clocking and test is independent of the tester capabilities since the internal PLL is used [2]. These at-speed scan patterns are popular today and several other newer types of scan patterns are gaining in usage. The growth in scan patterns has a big impact on test time and cost. Embedded scan compression techniques were developed to enable all the additional scan pattern types to be applied but without any additional tester time or cost [3]. They embed additional logic between the devices IO and scan chains. This logic acts as a transform function to take tester data and expand it to many short internal scan chains that ensure detection of targeted faults. Scan cell values that do not contribute to detection for that pattern are loaded with random values from the embedded logic instead of storing data on the tester. As a result, the tester loads and verifies values similar to normal scan test patterns but the load and unload time is fifty to one hundred times faster. The highest level of test quality is possible because the patterns are deterministic, specifically targeting faults, and due to the compression all the pattern types can be applied without cost implications. The need to apply more test patterns has driven the usage of embedded compression to be more popular than traditional scan. Figure 4. Embedded deterministic test enables high quality targeted pattern but with 100x fewer tester cycles per pattern. VI. BOUNDARY SCAN AND HIGHER LEVEL TEST Some IC test structures are primarily used for higher level testing. Boundary scan technology was developed to provide a simple method of testing for board-level (or MCM) manufacturing defects. A test structure is added to the IC IO pins with a controller. A four to five pin test access port (TAP) controls a state machine that operates the boundary scan test modes. Boundary scan test is similar to scan, except the control and observability are via boundary scan cells placed at each of the device’s functional IO. The boundary scan test process consists of loading values into the boundary scan registers, applying them to the device outputs and onto the board interconnects, capturing the responses at other device pin inputs, and shifting out for verification. Thus, the board level manufacturing defects can be checked without having to understand the IC designs or propagate signals through them. In addition, the interface to thoroughly test the board is through a simple four to five pin standard port. Connecting to the various device IO signals is not necessary. Boundary scan is common on many commercial products and standardized as IEEE standard 1149.1. Figure 5. Board with two devices containing boundary scan
Often the boundary scan TAP controller is re-used to P1P2-P可X RPCT Cell manage other internal test modes and test logic such as memory BIST and logic BIST.These tests can be easily re- used and controlled at board and higher levels of integration BC_1Cell through the boundary scan TAP Scan_In 1 scan out 1 VII LOW PIN COUNT TEST sign co Even though ICs of have many device IO pins.there are many advantages to reducing the tester interface to very few TDI pins.When the tester interface requires just a few pins then it TAP Scen and is possible to test several devices in parallel -multisite TestKompress P01P02..=P0X testing.Multisite testing is very popular for IC test since it is a great efficiency improvement. Figure 6.Low pin count test interface for IC testing Using a traditional scan strategy distributes the scan cells between the scan chains.Thus,the more scan chains the VIII.DIAGNOSING TEST FAILURES shorter they are and the fewer cycles to load them.If the scan chains are reduced to simplify the tester interface then they IC fabrication sites take advantage of the huge amount of will be longer in length and the test cycles and test time will controllability and observability available through scan be longer.Logic BIST solves this problem by not needing a technology.The algorithms in scan ATPG tools can process tester interface other than to initiate the test and check the scan tester failures and reverse engineer the results to final status.Though there are some test quality limitations determine the source of the failure.Scan diagnostics tools with logic BIST since it randomly targets faults.For testing have been developed to the point that they not only can report specific paths or other deterministic faults,deterministic the defective internal gate port or interconnect but also can ATPG may be desired. show the location in the physical silicon.In addition,the Fortunately,the embedded compression techniques such diagnostics ATPG tools can often determine the type of as EDT [3]can use as few as one tester scan channel but still defect that occurred in the silicon such as bridge between apply the tests much faster and in fewer tester cycles than nets,opens,and more. traditional scan.This is possible due to the technique including many short internal scan chains and transforming compressed data to the necessary scan cells during pattern IX TAKING ADVANTAGE OF IC TEST FEATURES loads.Some studies show that reducing a traditional scan approach from 32 scan chains to one embedded compression IC test continues to evolve but is generally at a very channel at the same time reduces the test cycles and test time mature state with reliable and high quality parts being by 8x [5].The IC IO pins do not need to be directly delivered after testing.DPM rates of only 100 or less are contacted by the tester because the boundary scan cells are possible with the existing test methods.Structured DFT such converted into scan chains during a special reduced pin count as scan technology breaks down the complexity of an IC into test(RPCT)mode [4]. smaller easier to test components.Even techniques to reduce The LPCT strategy can be controlled by a few pins as test application time and the tester interface exist and are well shown in the figure below or controlled completely through understood.There is a potential to take advantage of these IC the standard boundary scan TAP interface.Thus,higher test methods and apply similar strategies to higher levels of levels of assembly have the potential to perform detailed integration. device testing through a standard interface. REFERENCES [1]M.Beck,et.,al.,Logic Design for On-Chip Test Clock Generation- Implementation Details and Impact on Delay Test Quality",DATE 2005. [2☒] Boyer J,et al.,"Reducing The Design Impact Of DFT In The Nanometer Era",Electronic Design,Oct 2006. [3]J.Rajski,et al.,"Embedded Deterministic Test for Low Cost Manufacturing Test,"Proc.Int'l Test Conf.(ITC 02),IEEE Press, 2002,Pp.301-310. [4]J.Jahangiri,et al.,"Achieving High Test Quality with Reduced Pin Count Testing,"ATS 2005. [5]R.Press,"High Quality Test with Minimal Pins,"EDA Tech Forum Magazine,March 2008
Often the boundary scan TAP controller is re-used to manage other internal test modes and test logic such as memory BIST and logic BIST. These tests can be easily reused and controlled at board and higher levels of integration through the boundary scan TAP. VII. LOW PIN COUNT TEST Even though ICs of have many device IO pins, there are many advantages to reducing the tester interface to very few pins. When the tester interface requires just a few pins then it is possible to test several devices in parallel – multisite testing. Multisite testing is very popular for IC test since it is a great efficiency improvement. Using a traditional scan strategy distributes the scan cells between the scan chains. Thus, the more scan chains the shorter they are and the fewer cycles to load them. If the scan chains are reduced to simplify the tester interface then they will be longer in length and the test cycles and test time will be longer. Logic BIST solves this problem by not needing a tester interface other than to initiate the test and check the final status. Though there are some test quality limitations with logic BIST since it randomly targets faults. For testing specific paths or other deterministic faults, deterministic ATPG may be desired. Fortunately, the embedded compression techniques such as EDT [3] can use as few as one tester scan channel but still apply the tests much faster and in fewer tester cycles than traditional scan. This is possible due to the technique including many short internal scan chains and transforming compressed data to the necessary scan cells during pattern loads. Some studies show that reducing a traditional scan approach from 32 scan chains to one embedded compression channel at the same time reduces the test cycles and test time by 8x [5]. The IC IO pins do not need to be directly contacted by the tester because the boundary scan cells are converted into scan chains during a special reduced pin count test (RPCT) mode [4]. The LPCT strategy can be controlled by a few pins as shown in the figure below or controlled completely through the standard boundary scan TAP interface. Thus, higher levels of assembly have the potential to perform detailed device testing through a standard interface. Figure 6. Low pin count test interface for IC testing. VIII. DIAGNOSING TEST FAILURES IC fabrication sites take advantage of the huge amount of controllability and observability available through scan technology. The algorithms in scan ATPG tools can process scan tester failures and reverse engineer the results to determine the source of the failure. Scan diagnostics tools have been developed to the point that they not only can report the defective internal gate port or interconnect but also can show the location in the physical silicon. In addition, the diagnostics ATPG tools can often determine the type of defect that occurred in the silicon such as bridge between nets, opens, and more. IX. TAKING ADVANTAGE OF IC TEST FEATURES IC test continues to evolve but is generally at a very mature state with reliable and high quality parts being delivered after testing. DPM rates of only 100 or less are possible with the existing test methods. Structured DFT such as scan technology breaks down the complexity of an IC into smaller easier to test components. Even techniques to reduce test application time and the tester interface exist and are well understood. There is a potential to take advantage of these IC test methods and apply similar strategies to higher levels of integration. REFERENCES [1] M. Beck, et., al., ” Logic Design for On-Chip Test Clock Generation – Implementation Details and Impact on Delay Test Quality”, DATE 2005. [2] Boyer J, et al., “Reducing The Design Impact Of DFT In The Nanometer Era”, Electronic Design, Oct 2006. [3] J. Rajski, et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,” Proc. Int’l Test Conf. (ITC 02), IEEE Press, 2002, pp. 301-310. [4] J. Jahangiri, et al., “Achieving High Test Quality with Reduced Pin Count Testing,” ATS 2005. [5] R. Press, “High Quality Test with Minimal Pins,” EDA Tech Forum Magazine, March 2008
