《数字集成电路 Digital Integrated Circuit》课程教学资源（阅读资料）IC testing_An introduction to IC testing

An introduction to IC testing Far from being an adjunct to the production of integrated circuits,stage-by-stage testing represents a vital,and highly complex,part of the manufacturing process Frederick Van Veen Teradyne,Inc. IC testing has evolved from the patterns established years into the past for the origins of the patterns that some years ago in the production of semiconductors. have unfolded. Since manual testing cannot meet the complex needs The first automatic semiconductor test equipment to be indigenous to IC manufacture,highly sophisticated marketed commercially was manually programmed to instruments and test systems have developed that supply the proper biases,limits,and classification cri- are automatically programmed by computer,tape,or terions.Once programmed,the instruments were fully printed-circuit card.This article focuses on many of automatic in operation,the chief restriction on test rate the problems encountered and techniques employed, being the speed with which an operator could insert and also the requirements imposed on automatic IC transistors or diodes into the test socket and place them in testing systems. bins according to test results.Automatic handling equip- ment was soon introduced to perform both of these func- tions,and multiplexers were developed to give the test equipment even greater leverage. More than 300 million monolithic integrated circuits The manually programmed semiconductor tester sur- will have been sold in the United States during 1971,and vives in the form of instruments used for the incoming a conservative guess on industry-wide yield would lead inspection and evaluation of transistors,diodes,and,to a one to think that well over a billion chips were tested in very limited degree,ICs.It represents a practical approach order to produce these 300 million marketable ICs. to the problem of testing relatively small quantities of Each good circuit,in the course of its travel from wafer to devices,each of which requires a relatively small number end use,is probably tested an average of three times,and of tests.Most IC testing,however,involves complexity each test involves the qualification of many circuit func- beyond the practical limitations of manual programming. tions and parameters. This situation has led to the development of the test Without carrying this exercise to extremes,it is obvious equipment on which most attention is focused these that the integrated circuit has brought with it a tidal days-instruments and test systems automatically pro- wave of testing.Or,to turn the picture around,the intro- grammed by computer,tape,or printed-circuit card. duction of automatic equipment capable of making tens The computer,of course,offers not only test-plan storage of thousands of tests on a device in a few seconds has but also the important ability to base the conditions of made the integrated circuit commercially viable. one test on the results of a previous test.The computer Because IC testing is in the mainstream of the produc- (and in particular the minicomputer)has become a major tion process,it is very much in the mainstream of the element in the IC testing picture,and it is typical of our chronic IC cost/price competition.For this reason the bootstrap technology that the minicomputer is in a very technology of IC testing is always colored by economic real sense a product of its own making. considerations.It is usually far more important to Figure 1 is a generalized clock diagram of a com- accommodate another multiplexed test station than it is puter-controlled Ic test system,as represented by a to add another digit of resolution. number of commercial equipments.The test program is loaded into the computer via paper or magnetic tape Evolution or by punched cards.Instructions from the computer IC testing is,of course,only a logical extension of are sent to an interface or control unit,which passes transistor and diode testing,so we must look about ten them along to the appropriate elements of the system. 28 IEEE spectrum DECEMBER 1971

An introduction to IC testing Far from being an adjunct to the production of integrated circuits, stage-by-stage testing represents a vital, and highly complex, part of the manufacturing process Frederick Van Veen Teradyne, Inc. IC testing has evolved from the patterns established years into the past for the origins of the patterns that some years ago in the production of semiconductors. have unfolded. Since manual testing cannot meet the complex needs The first automatic semiconductor test equipment to be indigenous to IC manufacture, highly sophisticated marketed commercially was manually programmed to instruments and test systems have developed that supply the proper biases, limits, and classification cri￾are automatically programmed by computer, tape, or terions. Once programmed, the instruments were fully printed-circuit card. This article focuses on many of automatic in operation, the chief restriction on test rate the problems encountered and techniques employed, being the speed with which an operator could insert and also the requirements imposed on automatic IC transistors or diodes into the test socket and place them in testing systems. bins according to test results. Automatic handLing equip￾ment was soon introduced to perform both of these func￾tions, and multiplexers were developed to give the test equipment even greater leverage. More than 300 million monolithic integrated circuits The manually programmed semiconductor tester sur￾will have been sold in the United States during 1971, and vives in the form of instruments used for the incoming a conservative guess on industry-wide yield would lead inspection and evaluation of transistors, diodes, and, to a one to think that well over a billion chips were tested in very limited degree, ICs. It represents a practical approach order to produce these 300 million marketable ICs. to the problem of testing relatively small quantities of Each good circuit, in the course of its travel from wafer to devices, each of which requires a relatively small number end use, is probably tested an average of three times, and of tests. Most IC testing, however, involves complexity each test involves the qualification of many circuit func- beyond the practical limitations of manual programming. tions and parameters. This situation has led to the development of the test Without carrying this exercise to extremes, it is obvious equipment on which most attention is focused these that the integrated circuit has brought with it a tidal days-instruments and test systems automatically pro￾wave of testing. Or, to turn the picture around, the intro- grammed by computer, tape, or printed-circuit card. duction of automatic equipment capable of making tens The computer, of course, offers not only test-plan storage of thousands of tests on a device in a few seconds has but also the important ability to base the conditions of made the integrated circuit commercially viable. one test on the results of a previous test. The computer Because IC testing is in the mainstream of the produc- (and in particular the minicomputer) has become a major tion process, it is very much in the mainstream of the element in the IC testing picture, and it is typical of our chronic IC cost/price competition. For this reason the bootstrap technology that the minicomputer is in a very technology of IC testing is always colored by economic real sense a product of its own making. considerations. It is usually far more important to Figure 1 is a generalized clock diagram of a com￾accommodate another multiplexed test station than it is puter-controlled IC test system, as represented by a to add another digit of resolution. number of commercial equipments. The test program is loaded into the computer via paper or magnetic tape Evolution or by punched cards. Instructions from the computer IC testing is, of course, only a logical exten.sion of are sent to an interface or control unlit, which passes transistor and diode testing, so we must look about ten them along to the appropriate elements of the system. 28 IEEE spectrum DECEMBER 1971

Tape or cards Test statlor Computer Control Buffer D/A Multiplexe Test unit converter station Test station FIGURE 1.Basic con- Operator A/D figuration of a com- keyboard Buffer converte puter-controlled IC test system. IC under test FIGURE 2.Block dia- gram of comparison- type functional tester. Pattern generator Reject Exclusive OR lamp Π几u Instructions to apply stimuli to the IC are buffered, application among producers and high-volume users of converted into analog voltages,and delivered to the ICs.At the other end of the scale is the comparison-type pins at the test sockets of multiplexed test stations (or to tester,shown in block-diagram form in Fig.2.Here a wafer probers),which are time-shared under computer binary or random pattern is applied to the device under control.The output functions of the IC are converted test and at the same time to a reference unit having the into digital form,buffered,and returned to the control same truth table as the unknown.The outputs are com- unit and computer for processing.The operator exercises pared and a reject lamp lights when they differ.Instru- overall control of the system by teletypewriter keyboard ments using this technique are relatively inexpensive and commands. are preferred for incoming inspection of ICs in low or Systems of the type shown in Fig.1 typically cost moderate volume. from S50 000 to well over $100 000 and find greatest In some applications,especially those in which in- Van Veen-An introduction to IC testing 29

FIGURE 1. Basic con￾figuration of a com￾puter-controlled IC test system. IC under test FIGURE 2. Block dia￾gram of comparison￾type functional tester. Pattern r Il*l * e r l l | | ~~~~~~~~~~~Exclusive OR Rlamrnpt Reference Instructions to apply stimuli to the IC are buffered, application among producers and high-volume users of converted into analog voltages, and delivered to the ICs. At the other end of the scale is the comparison-type pins at the test sockets of multiplexed test stations (or to tester, shown in block-diagram form in Fig. 2. Here a wafer probers), which are time-shared under computer binary or random pattern is applied to the device under control. The output functions of the IC are converted test and at the same time to a reference unit having the into digital form, buffered, and returned to the control same truth table as the unknown. The outputs are com￾unit and computer for processing. The operator exercises pared and a reject lamp lights when they differ. Instru￾overall control of the system by teletypewriter keyboard ments using this technique are relatively inexpensive and commands. are preferred for incoming inspection of ICs in low or Systems of the type shown in Fig. 1 typically cost moderate volume. from $50 000 to well over $100 000 and find greatest In some applications, especially those in which in￾Van Veen-An introduction to IC testing 29

Driver/comparator module (1 per channel) Voltage reterence Current-limit hg reference Parametric Voltage measurement reference A system Current-limit Kelvin reterence Drivers Voltage reference Current-limit Parametric reterence Voltage system reference Kelvin Current-limit reference High limit High/iow logic Sold state Low limit Reed relay Relevance Voltage Comparators nth result 0n+4 0n+3 on+2 Transterred unde 0n+1 sottware contro! o nth channel FIGURE 3.Driver/comparator t switching,as employed in the Teradyne J283 computer-opera- ted Ic test system. coming inspection is included,the ideal system or instru- Clock-rate testing,which refers to the functional ment would be versatile enough to handle bipolar and testing of MOS digital circuits at their maximum and metal oxide semiconductor (MOS)devices,both digital minimum repetition rates. and linear.Although such"universal"systems have been Parametric testing,which measures IC voltages and attempted,they are usually hybridizations of individual currents at high accuracy and a relatively low test rate. special-purpose test systems,based on the sharing of Direct-current parametric testing refers to tests in which certain common elements (e.g.,the controlling com- the inputs are maintained until the outputs reach a stable puter). state.Pulse parametric (or dynamic)testing refers to For all practical purposes,however,the testing of tests of the time-related properties of an IC. bipolar,MOS,and linear ICs can be considered three To summarize,the two chief classes of digital-IC distinct subjects.The technologies are different.and the testing are functional (high rate,low accuracy)and three types of devices represent three subindustries,each parametric (low rate,high accuracy).Note that the of which can afford to optimize its production processes. recording of a parametric value is nor essential to para- metric testing. Defining terms After some years of semantic chaos,the lexicon of The testing of digital bipolar ICs IC testing is beginning to stabilize.The principal branches The digital bipolar class represents by far the largest of the tree are as follows: segment of IC production today,and testing techniques Functional testing,which checks the truth table (or are somewhat more standardized than they are for other a subset of it)of a digital IC by applying a sequence of device families.The usual pattern is:functional testing input words at nominal voltage levels and checking to find catastrophic failures caused by improper packag- the corresponding output words.Functional testing ing,bonding,metalization,photolithography,die mount- usually involves a large number of tests and is therefore ing,etc.and dc and pulse parametric testing to uncover performed at the highest machine speed,at the expense of failures due to surface or oxide defects,such as channeling accuracy. pinholes,etc.Although virtually all ICs are tested func- 30 IEEE spectrum DECEMBER 1971

_-_~~~ ~( pe chanversl)eli ___reference z tv Kli Current-limit _ KlT reference Kelvin _V_oHltagehmit S w _ _ E Sobd state ....._refereance - Reed relay Transferred undee n + 1 l|software control _ nth channel _ FIGURE 3. Driver/comparator crier switching, as employed in the _ ___ Teradyne J283 computer-opera- _ ted IC test system. coming inspection is included, the ideal system or instru- Clock-rate testing, which refers to the functional ment would be versatile enough to handle bipolar and testing of MOS digitatl circuits at their maximum and metal oxide semiconductor (MOS) devices, both digital minimum repetition rates. and linear. Although such "universal" systems have been Parametric testing, which measures IC voltages and attempted, they are usually hybridizations of individual currents at high accuracy and a relatively low test rate. special-purpose test systems, based on the sharing of Direct-current parametric testing refers to tests in which certain common elements (e.g., the controlling com- the inputs are maintained until the outputs reach a stable puter). state. Pulse parametric (or dynamic) testing refers to For all practical purposes, however, the testing of tests ofthe time-related properties ofanlIC. bipolar, MOS, and linear ICs can be considered three To summarize, the two chief classes of digital-IC distinct subjects. The technologies are different, and the testing are functional (high rate, low accuracy) and three types of devices represent three subindustries, each parametric (low rate, high accuracy). Note that the of which can afford to optimize its production processes. recording of a parametric value is not essential to para￾metric testing. Defining terms After some years of semantic chaos, the lexicon of The testing of digital bipolar lCs IC testing is beginning to stabilize. The principal branches The digital bipolar class represents by far the largest ofthe tree are asrfollows: segment of IC production today, and testing techniques Functional testing, which checks the truth table (or are somewhat more standardized than they are for other a subset of it) of a digital IC by applying a sequence of device families. The usual pattern is: functional testing input words at nominal voltage levels and checking to find catastrophic failures caused by improper packag￾the corresponding output words. Functional testing ing, bonding, metalization, photolithography, die mount￾usually involves a large number of tests and is therefore ing, etc.; and dc and pulse parametric testing to uncover performed at the highest machine speed, at the expense of failures due to surface or oxide defects, such as channeling. accuracy. pinholes, etc. Although virtually all ICs are tested func￾logicIEEE spectrum DECEMBER t97a

tionally and for de characteristics,pulse parametric or The functional-testing end of a computer-operated IC dynamic testing is performed chiefly on fast transistor- test system is diagrammed in Fig.3.In this system transistor logic (TTL)or emitter-coupled logic (ECL) (Teradyne's J283 "SLOT"system),each pin of the IC devices. under test is connected to a module that contains two It is important to note that these three types of tests- pairs of programmable"drivers"and a pair of compara- functional,dc parametric,and pulse parametric-are tors.The drivers are actually fast solid-state switches related to distinctly different properties of an IC,and that gate power from buffered digital-to-analog (D/A) that a test sequence of one type only,no matter how voltage sources.The voltage levels from these sources thorough,cannot provide adequate device characteriza- are assigned by computer control,and it is the function tion. of the drivers to switch these voltages into the circuit Functional testing.A digital IC responds to a combina- quickly while preserving waveform integrity.All four tion of high and low inputs (I's and 0's)by producing drivers have programmable current limiting to prevent a certain combination of high and low outputs.Func- device damage. tional testing ensures that the combinations are as they The two comparators receive programmable reference should be for the logic in question.For combinatorial voltages from the buffered source for use in determining devices in which there are relatively few inputs,one can whether IC output levels are above or below specified achieve thorough functional testing through the brute- limits.Note that during functional testing each pin is force approach of exercising all input combinations. always connected to both the driver and detector sec- This approach breaks down,however,when the IC tions of the module,and that only a software command under test contains sequential logic,where the outputs is needed to change a given channel from an input to an are a function not only of the input combination but output or vice versa,an important consideration in the also of the order in which the various inputs are ex- testing of certain ICs having pins that serve both func- ercised. tions.This arrangement also makes it possible for the The presence of sequential logic raises the number of system to apply a programmable load to an output pin possible input combinations and sequences far beyond during testing. the practical reach of even the fastest testers,and the The output of either comparator is observed or not testing problem then becomes one of choosing the best of depending on the presence or absence of a "relevance" the available compromises. software command.Thus,where one wishes to exercise One compromise approach is based on the application an IC but ignore the logic outputs (as,for example,when of random patterns to the inputs and the statistical prob- preconditioning an IC),the comparator output is simply ability that these will test the device adequately.The made nonrelevant.Where it is relevant,the system may shortcomings of this approach are that (1)the chances of be programmed to look for failures in any of three ways testing for every possible failure mode are extremely re- It can look at each pin ("nth result"),sending pass-fail mote,(2)a random pattern makes no allowance for time information back to the computer.Usually,however, delays that flip-flops or other sequential devices may it is not necessary to isolate failures down to pins and it is require at various points in their operation,and (3) sufficient to know that some pin failed at a given point the random pattern does not take into account the neces- in the test sequence.Thus all the nth-result indications sity for "initializing"certain ICs-that is,setting them can be logically oRed to give a "present result."When to some known state before testing can begin. long test patterns are applied even this method (which Alternatively,one can algorithmically generate test requires communication with the computer at each step) patterns designed to detect all the failure modes intrinsic is impractical.In such cases the "present result"indica- to the logic at hand.Software can be developed that tion is automatically strobed into the"cumulative result" will iteratively apply patterns,verify that given failure memory after each logic sentence.The cumulative result modes are or are not detected,and modify the patterns tells the operator that the IC failed somewhere along the accordingly.This is a complex process and one on which line,which is very often the only information that is of much effort is being spent.Commercial pattern-genera- interest. tion services have sprung up in recent years to satisfy the Clock-rate testing.MOS clock-rate testing is ana- growing demand for solutions to the testing problems logous to functional testing,with one important differ- associated with large-scale integration. ence:In bipolar functional testing,the test speed is very In the never-ending search for right combinations of slow compared with the maximum speed at which the IC I's and 0's,it is all too easy to overlook the fact that an will operate,and thus is not a consideration.Clock-rate IC under test sees not 1's and 0's,but fast transitions MOS testing,on the other hand,is conducted near the of voltage or current.These transitions have to be fast maximum frequency of the device,which,for today's enough to simulate the inputs the device will encounter faster devices,is in the region around 5 MHz,with 10 in its end use and to represent decisive changes of state MHz over the not-too-distant horizon.At the other end (i.e.,a transition should not be so slow as to linger in of the spectrum,measurement of the "stay-alive"time the turn-on region of a device),but they should not be so (or minimum operating frequency)of the device may fast as to produce unacceptable overshoot,ringing,or require a test frequency as low as 1 Hz. crosstalk,which can result in double-clocking of devices, Not only must the MOS test system be able to supply channel interference problems,etc.An oscilloscope high-frequency test signals,it also must supply several connected to the test points of a wafer prober will sets of them (phases),each precisely settable with respect speak volumes about an IC test system's ability to test to the others.The number of phases needed depends on ICs reliably.Unless one can take a clean test signal the types of devices to be tested;common requirements for granted,he can never be confident of his test results, are for two or four phases with a phase resolution of 1 ns no matter how elegant the test patterns. or better.The ability to manipulate phases with respect to Van Veen-An introduction to IC testing 31

tionally and for dc characteristics, pulse parametric or The functional-testing end of a computer-operated IC dynamic testing is performed chiefly on fast transistor- test system is diagrammed in Fig. 3. In this system transistor logic (TTL) or emitter-coupled logic (ECL) (Teradyne's J283 "SLOT" system), each pin of the IC devices. under test is connected to a module that contains two It is important to note that these three types of tests- pairs of programmable "drivers" and a pair of compara￾functional, dc parametric, and pulse parametric-are tors. The drivers are actually fast solid-state switches related to distinctly different properties of an IC, and that gate power from buffered digital-to-analog (D/A) that a test sequence of one type only, no matter how voltage sources. The voltage levels from these sources thorough, cannot provide adequate device characteriza- are assigned by computer control, and it is the function tion. of the drivers to switch these voltages into the circuit Functional testing. A digital IC responds to a combina- quickly while preserving waveform integrity. All four tion of high and low inputs (l's and 0's) by producing drivers have programmable current limiting to prevent a certain combination of high and low outputs. Func- device damage. tional testing ensures that the combinations are as they The two comparators receive programmable reference should be for the logic in question. For combinatorial voltages from the buffered source for use in determining devices in which there are relatively few inputs, one can whether IC output levels are above or below specified achieve thorough functional testing through the brute- limits. Note that during functional testing each pin is force approach of exercising all input combinations. always connected to both the driver and detector sec￾This approach breaks down, however, when the IC tions of the module, and that only a software command under test contains sequential logic, where the outputs is needed to change a given channel from an input to an are a function not only of the input combination but output or vice versa, an important consideration in the also of the order in which the various inputs are ex- testing of certain ICs having pins that serve both func￾ercised. tions. This arrangement also makes it possible for the The presence of sequential logic raises the number of system to apply a programmable load to an output pin possible input combinations and sequences far beyond during testing. the practical reach of even the fastest testers, and the The output of either comparator is observed or not, testing problem then becomes one of choosing the best of depending on the presence or absence of a "relevance" the available compromises. software command. Thus, where one wishes to exercise One compromise approach is based on the application an IC but ignore the logic outputs (as, for example, when of random patterns to the inputs and the statistical prob- preconditioning an IC), the comparator output is simply ability that these will test the device adequately. The made nonrelevant. Where it is relevant, the system may shortcomings of this approach are that (1) the chances of be programmed to look for failures in any of three ways. testing for every possible failure mode are extremely re- It can look at each pin ("nth result"), sending pass-fail mote, (2) a random pattern makes no allowance for time information back to the computer. Usually, however, delays that flip-flops or other sequential devices may it is not necessary to isolate failures down to pins and it is require at various points in their operation, and (3) sufficient to know that some pin failed at a given point the random pattern does not take into account the neces- in the test sequence. Thus all the nth-result indications sity for "initializing" certain ICs-that is, setting them can be logically oRed to give a "present result." When to some known state before testing can begin. long test patterns are applied even this method (which Alternatively, one can algorithmically generate test requires communication with the computer at each step) patterns designed to detect all the failure modes intrinsic is impractical. In such cases the "present result" indica￾to the logic at hand. Software can be developed that tion is automatically strobed into the "cumulative result" will iteratively apply patterns, verify that given failure memory after each logic sentence. The cumulative result modes are or are not detected, and modify the patterns tells the operator that the IC failed somewhere along the accordingly. This is a complex process and one on which line, which is very often the only information that is of much effort is being spent. Commercial pattern-genera- interest. tion services have sprung up in recent years to satisfy the Clock-rate testing. MOS clock-rate testing is ana￾growing demand for solutions to the testing problems logous to functional testing, with one important differ￾associated with large-scale integration. ence: In bipolar functional testing, the test speed is very In the never-ending search for right combinations of slow compared with the maximum speed at which the IC l's and 0's, it is all too easy to overlook the fact that an will operate, and thus is not a consideration. Clock-rate IC under test sees not l's and 0's, but fast transitions MOS testing, on the other hand, is conducted near the of voltage or current. These transitions have to be fast maximum frequency of the device, which, for today's enough to simulate the inputs the device will encounter faster devices, is in the region around 5 MHz, with 10 in its end use and to represent decisive changes of state MHz over the not-too-distant horizon. At the other end (i.e., a transition should not be so slow as to linger in of the spectrum, measurement of the "stay-alive" time the turn-on region of a device), but they should not be so (or minimum operating frequency) of the device may fast as to produce unacceptable overshoot, ringing, or require a test frequency as low as 1 Hz. crosstalk, which can result in double-clocking of devices, Not only must the MOS test system be able to supply channel interference problems, etc. An oscilloscope high-frequency test signals, it also must supply several connected to the test points of a wafer prober will sets of them (phases), each precisely settable with respect speak volumes about an IC test system's ability to test to the others. The number of phases needed depends on ICs reliably. Unless one can take a clean test signal the types of devices to be tested; common requirements for granted, he can never be confident of his test results, are for two or four phases with a phase resolution of 1 ns no matter how elegant the test patterns. or better. The ability to manipulate phases with respect to Van Veen-An introduction to IC testing 31

one another adds another dimension to the use of test Whereas functional testing usually involves voltage patterns in LSI testing;an alternative to the use of many swings of 30 volts or less,dc parametric test systems long patterns may be the application of a few worst-case typically can force 100 volts or more.In systems having patterns under varying phase relationships. both functional and parametric test sections,break- Great demands are placed on the drivers of an MOS before-make switching from one to the other is required test system.They must be able to swing 30 volts,at a so that the power available for parametric testing cannot slope of 1 ns/V or better,with minimum overshoot, inadvertently damage the functional-test drivers and ringing,or crosstalk,through cables to automatic hand- comparators. lers or wafer probers.Satisfactory performance results One of the most interesting and significant recent once one recognizes the practical necessity of such cables developments in IC testing has been the growing em- between drivers and the device under test and designs phasis placed on pulse parametric,or dynamic,testing the test system accordingly,using impedance-matching Several factors lie behind this trend.First,speed margins techniques to minimize the effects of cable capacitance. represent the essential differences(and therefore the price Parametric testing.Functional testing,even when premiums)between one device type and another.Second, exhaustively complete,cannot be relied on to determine these differences in operating speed cannot be verified whether an IC will operate in its end use.The test system by dc and functional testing.Third,equipment that can cannot simulate all of the possible circuits in which a reliably measure dynamic performance on a production- device may be used,and it is therefore necessary to line basis has become available only fairly recently measure certain parameters and to compare them against Pulse parametric testing refers to a limited number of specified limits.These measurements will define the time-interval measurements-principally those of propa- fanout capabilities of the device,as well as leakage gation delay,rise time,and fall time.For the fastest current,power dissipation,etc.Usually a few parameters digital devices,these intervals are so short as to challenge are measured for each of a number of input conditions. the state of the measurement art.A test system handling The technique for making dc parametric tests is that ECL and fast TTL logic must be able to measure a of forcing a voltage or current at an input and comparing propagation delay of a nanosecond repeatedly and with the resulting output current or voltage against a limit. a precision of 10 picoseconds. The test result can be taken as a simple go/no-go indica- Some of the key issues in pulse parametric testing have tion,or A/D conversion techniques can be applied to to do with the way parameters are defined and speci- record the actual value of the parameter in question. fied.Rise time,for example,is often defined as the time One such technique is a software-directed sequential it takes a voltage to rise from 10 to 90 percent of its approximation in which a series of go/no-go comparisons maximum value,but,given a pulse with any overshoot is made,the reference converging on the unknown. or ringing,the maximum value and therefore the rise- Since the emphasis in parametric testing is on accuracy, time boundaries are uncertain.A much more rigorous precautions are taken in equipment design to eliminate definition would prescribe actual voltage levels as the stray capacitance and spurious ground currents.Kelvin boundaries for rise and fall times and propagation delay. connections are generally used,in conjunction with The parameters involved in a typical pulse parametric driven guard shields,to minimize cable charging currents test are defined in Fig.4,which illustrates the dynamic that could introduce time-constant delays in circuit characteristics of a typical TTL gate.The rise and fall stabilization. times of the input pulse,t and t,are defined in terms Because a parametric test generally takes much longer of actual voltage levels,not percentages;t and t than a functional test,the interplay between the two are the propagation times from high to low and from low types of test directly affects productivity.The programmer to high levels,respectively,and both are usually specified of a computer-operated system has several options and tested. available to him:He can run all functional tests first, Note that the accuracy with which one can define fpz in order to screen out catastrophic rejects before para and fPLa depends on the accuracy with which the 1.5-volt metric testing;or he may make certain critical parametric thresholds are known,and this in turn is a function of tests first;or he may functionally test,branching into the slope of the voltage transitions (a slow transition a parametric sequence upon failure. rate amplifies any threshold error).Input transition rate should therefore be specified,along with pulse amplitudes and durations Once the characteristics of the input pulse have been FIGURE 4.Dynamic properties of a 5400-series TTL gate specified,the problem becomes one of ensuring that these Pulse parametric system measures rise and fall times characteristics are achieved,not at the output of the and propagation delays tpaL and tpLB. pulse generator but at the test socket.In a self-calibrating system each test pulse is first measured at the test socket tr长 and the pulse generator is automatically adjusted to produce the desired characteristics at the socket. 2.7v 2.7V Early dynamic measurements on ICs were made by 1.5V 1.5V 0.7V 0.7V sampling techniques similar to these well established in high-frequency laboratory measurements.More recently, thet“real-time”ort“single-shot”technique,in which a single time interval is measured in terms of the amount of charge absorbed by a reference capacitor during that time,has achieved widespread acceptance and appears now to predominate. IEEE spectrum DECEMBER 1971

one another adds another dimension to the use of test Whereas functional testing usually involves voltage patterns in LSI testing; an alternative to the use of many swings of 30 volts or less, dc parametric test systems long patterns may be the application of a few worst-case typically can force 100 volts or more. In systems having patterns under varying phase relationships. both functional and parametric test sections, break￾Great demands are placed on the drivers of an MOS before-make switching from one to the other is required test system. They must be able to swing 30 volts, at a so that the power available for parametric testing cannot slope of 1 ns/V or better, with minimum overshoot, inadvertently damage the functional-test drivers and ringing, or crosstalk, through cables to automatic hand- comparators. lers or wafer probers. Satisfactory performance results One of the most interesting and significant recent once one recognizes the practical necessity of such cables developments in IC testing has been the growing em￾between drivers and the device under test and designs phasis placed on pulse parametric, or dynamic, testing. the test system accordingly, using impedance-matching Several factors lie behind this trend. First, speed margins techniques to minimize the effects of cable capacitance. represent the essential differences (and therefore the price Parametric testing. Functional testing, even when premiums) between one device type and another. Second, exhaustively complete, cannot be relied on to determine these differences in operating speed cannot be verified whether an IC will operate in its end use. The test system by dc and functional testing. Third, equipment that can cannot simulate all of the possible circuits in which a reliably measure dynamic performance on a production￾device may be used, and it is therefore necessary to line basis has become available only fairly recently. measure certain parameters and to compare them against Pulse parametric testing refers to a limited number of specified limits. These measurements will define the time-interval measurements-principally those of propa￾fanout capabilities of the device, as well as leakage gation delay, rise time, and fall time. For the fastest current, power dissipation, etc. Usually a few parameters digital devices, these intervals are so short as to challenge are measured for each of a number of input conditions. the state of the measurement art. A test system handling The technique for making dc parametric tests is that ECL and fast TTL logic must be able to measure a of forcing a voltage or current at an input and comparing propagation delay of a nanosecond repeatedly and with the resulting output current or voltage against a limit. a precision of 10 picoseconds. The test result can be taken as a simple go/no-go indica- Some of the key issues in pulse parametric testing have tion, or A/D conversion techniques can be applied to to do with the way parameters are defined and speci￾record the actual value of the parameter in question. fied. Rise time, for example, is often defined as the time One such technique is a software-directed sequential it takes a voltage to rise from 10 to 90 percent of its approximation in which a series of go/no-go comparisons maximum value, but, given a pulse with any overshoot is made, the reference converging on the unknown. or ringing, the maximum value and therefore the rise￾Since the emphasis in parametric testing is on accuracy, time boundaries are uncertain. A much more rigorous precautions are taken in equipment design to eliminate definition would prescribe actual voltage levels as the stray capacitance and spurious ground currents. Kelvin boundaries for rise and fall times and propagation delay. connections are generally used, in conjunction with The parameters involved in a typical pulse parametric driven guard shields, to minimize cable charging currents test are defined in Fig. 4, which illustrates the dynamic that could introduce time-constant delays in circuit characteristics of a typical TTL gate. The rise and fall stabilization. times of the input pulse, tr and tf, are defined in terms Because a parametric test generally takes much longer of actual voltage levels, not percentages; tPHL and tpLH than a functional test, the interplay between the two are the propagation times from high to low and from low types of test directly affects productivity. The programmer to high levels, respectively, and both are usually specified of a computer-operated system has several options and tested. available to him: He can run all functional tests first, Note that the accuracy with which one can define tPHL in order to screen out catastrophic rejects before para- and tPLH depends on the accuracy with which the 1.5-volt metric testing; or he may make certain critical parametric thresholds are known, and this in turn is a function of tests first; or he may functionally test, branching into the slope of the voltage transitions (a slow transition a parametric sequence upon failure. rate amplifies any threshold error). Input transition rate should therefore be specified, along with pulse amplitudes and durations. Once the characteristics of the input pulse have been FIGURE 4. Dynamic properties of a 5400-series TTL gate. specified, the problem becomes one of ensuring that these Pulse parametric system measures rise and fall times characteristics are achieved, not at the outptut of the and propagation delays tpHL and tPLH. pulse generator but at the test socket. In a self-calibrating system each test pulse is first measured at the test socket ~ tr ~ ~ tf ~ and the pulse generator is automatically adjusted to | ~~~~~~~~~~produce ' r ' ' the desired characteristics at the socket. 2.7v 2.7VYv, ~~~~~Early dynamic measurements on ICs were made by I tPLH :E the "real-time' or "singie-shot" technique, in which a Jr - ~~~~~~~~~~~~~single ' | time interval is measured in terms of the amount ,, ,/ ~~~~~~~~of charge absorbed by a reference capacitor during that \ / ~~~~~~~~time, has achieved widespread acceptance and appears ~~~~~~~~now vOL S to predominate. 32 ~~~~~~~~~~~~~~~~~~~~~~~~~~IEEE spectrum DECEMBER 1971

To be useful on a production line,a dynamic test For production testing,the advantages of computer system must be compatible with automatic handling control are overwhelming.There is,in fact,no real al- equipment and probers,and here the normal problems of ternative;the number of parameters that may have to be preserving clean test waveforms are multiplied a thou- measured at one time or another is well beyond the reach sandfold because the pulses involved are extremely fast. of a hardware-only system.Even with computer-op- Another practical requirement is that dynamic tests be erated systems,the variations in test requirements are so performed along with functional and dc tests,in a single great that much of the test programming must take the insertion of the IC in the test socket. form of"performance boards,"which are special-pur- Despite many technological obstacles,dynamic testing pose plug-ins incorporating the output loads and circuits has now come of age.At least one computer maker needed to test a given family of devices. has turned to 100 percent dynamic testing of all ICs in An interesting sidelight is that linear ICs are much more incoming inspestion,in an effort to find dynamically thoroughly tested than their nonmonolithic predecessors. defective devices before they can be loaded on circuit Consider,for example,the list of tests performed by an boards.The price of discovering defective devices after automatic test system on a stereo demodulator in IC they already have been assembled in circuits is simply too form: great. 1.Power consumption. 2.Left and right output level The testing of semiconductor memories 3.Audio mute on and off thresholds. Semiconductor memories are functionally and para- 4.Audio mute attenuation. metrically tested like other ICs,but the fact that they have 5.Audio mute thump. fixed outputs somewhat simplifies the problem.Various 6.Channel balance. test patterns are used to ensure that the reading or the 7.Rejection tests for 19-and 38-kHz components writing of a bit of memory will not affect the logic in 8.Stereo separation. adjacent cells.One commonly used pattern is a checker- 9.Monaural distortion. board of 1's and 0's.Another is the floating of a 1 or a 0 10.Stereo distortion. from cell to cell while the adjacent cells are maintained 11.Lamp on and off threshold. in the opposite state.There are many variations on these 12.Stereo muting on and off threshold. themes. This entire complement of tests,plus an automatic Where only a limited number of memory types are to pilot-subcarrier phase adjustment,can be made in well be tested one may turn to a special-purpose memory under a second by a computer-operated test system. exerciser such as that shown in Fig.5.In this instrument, It is doubtful that any discrete-component stereo de- the Macrodata MD-100,the desired patterns are stored modulator was ever as thoroughly tested in production, on read-only memories and the device signal and timing a good deal of manual trimming and tweeking notwith- information is programmed on plug-in "personality standing. cards.” Although the more advanced consumer circuits must be The larger,computer-operated IC test system,on the tested by large computer-operated systems,simpler de- other hand,brings the many advantages of computer vices such as operational amplifiers,voltage regulators, control to memory testing.Most important of these is and comparators can be tested in incoming inspection by the ability to handle any semiconductor memory without small bench-type instruments,typically programmed by the need for additional equipment. plug-in circuit boards.One such instrument,the General The generation of test patterns for memories is simple Radio Type 1730 Linear Circuit Tester,is shown in Fig. in concept,but with even moderate-size memories the pattern length is long enough to be a consideration. Floating I's and 0's through a 256-bit memory requires more than 120 000 functional tests,which are too many for economical storage in core or for fast disk-to-core FIGURE 5.A noncomputer-operated tester for semi- transfer.One answer to this problem is on-line pattern conductor memories (the Macrodata MD-100). generation,which allows a test system to produce patterns as it tests,using only about 1200 words of minicomputer memory. The testing of linear ICs ◆0000000000900QQ000Q0000Q●￥ Until a year or so ago,"linear IC testing"meant,for all practical purposes,the testing of operational ampli- fiers,which in turn meant the measurement of the offset voltage,offset current,open-loop gain,power capability, ◆Q00000QQ666666656 common-mode rejection,and a few other dc character- istics of these devices.More recently,however,several other types of linear IC have begun to appear in volume, 00000009 many of them for consumer-electronics applications. Now linear IC testing includes the testing of circuits as diverse as voltage regulators and television chroma demodulators.Thus there is little that can be said of linear testing in general,beyond some observations on the types of test equipment commonly used. Van Veen-An introduction to IC testing

To be useful on a production line, a dynamic test For production testing, the advantages of computer system must be compatible with automatic handling control are overwhelming. There is, in fact, no real al￾equipment and probers, and here the normal problems of ternative; the number of parameters that may have to be preserving clean test waveforms are multiplied a thou- measured at one time or another is well beyond the reach sandfold because the pulses involved are extremely fast. of a hardware-only system. Even with computer-op￾Another practical requirement is that dynamic tests be erated systems, the variations in test requirements are so performed along with functional and dc tests, in a single great that much of the test programming must take the insertion of the IC in the test socket. form of "performance boards," which are special-pur￾Despite many technological obstacles, dynamic testing pose plug-ins incorporating the output loads and circuits has now come of age. At least one computer maker needed to test a given family of devices. has turned to 100 percent dynamic testing of all ICs in An interesting sidelight is that linear ICs are much more incoming inspeGtiOn, in an effort to find dynamically thoroughly tested than their nonmonolithic predecessors. defective devices before they can be loaded on circuit Consider, for example, the list of tests performed by an boards. The price of discovering defective devices after automatic test system on a stereo demodulator in IC they already have been assembled in circuits is simply too form: great. 1. Power consumption. 2. Left and right output level. The testing of semiconductor memories 3. Audio mute on and off thresholds. Semiconductor memories are functionally and para- 4. Audio mute attenuation. metrically tested like other ICs, but the fact that they have 5. Audio mute thump. fixed outputs somewhat simplifies the problem. Various 6. Channel balance. test patterns are used to ensure that the reading or the 7. Rejection tests for 19- and 38-kHz components. writing of a bit of memory will not affect the logic in 8. Stereo separation. adjacent cells. One commonly used pattern is a checker- 9. Monaural distortion. board of l's and 0's. Another is the floating of a I or a 0 10. Stereo distortion. from cell to cell while the adjacent cells are maintained 11. Lamp on and off threshold. in the opposite state. There are many variations on these 12. Stereo muting on and off threshold. themes. This entire complement of tests, plus an automatic Where only a limited number of memory types are to pilot-subcarrier phase adjustment, can be made in well be tested one may turn to a special-purpose memory under a second by a computer-operated test system. exerciser such as that shown in Fig. 5. In this instrument, It is doubtful that any discrete-component stereo de￾the Macrodata MD-100, the desired patterns are stored modulator was ever as thoroughly tested in production, on read-only memories and the device signal and timing a good deal of manual trimming and tweeking notwith￾information is programmed on plug-in "personality standing. cards." Although the more advanced consumer circuits must be The larger, computer-operated IC test system, on the tested by large computer-operated systems, simpler de￾other hand, brings the many advantages of computer vices such as operational amplifiers, voltage regulators, control to memory testing. Most important of these is and comparators can be tested in incoming inspection by the ability to handle any semiconductor memory without small bench-type instruments, typically programmed by the need for additional equipment. plug-in circuit boards. One such instrument, the General The generation of test patterns for memories is simple Radio Type 1730 Linear Circuit Tester, is shown in Fig. in concept, but with even moderate-size memories the pattern length is long enough to be a consideration. Floating l's and 0's through a 256-bit memory requires more than 120 000 functional tests, which are too many for economical storage in core or for fast disk-to-core FIGURE 5. A noncomputer-operated tester for semi￾transfer. One answer to this problem is on-line pattern conductor memories (the Macrodata MD-100). generation, which allows a test system to produce patterns as it tests, using only about 1200 words of minicomputer memory. The testing of linear ICs Until a year or so ago, "linear IC testing" meant, for all practical purposes, the testing of operational ampli￾fiers, which in turn meant the measurement of the offset voltage, offset current, open-loop gain, power capability, common-mode rejection, and a few other dc character￾istics of these devices. More recently, however, several other types of linear IC have begun to appear in volume, many of them for consumer-electronics applications. Now linear IC testing includes the testing of circuits as diverse as voltage regulators and television chroma __l_i___l_i_*_l_l_*___*____ demodulators. Thus there is little that can be said of linear testing in general, beyond some observations on the types of test equipment commonly used. Van Veen-An introduction to IC testing 33

6.This instrument is programmed by a plug-in card The number of stations and the level of independence containing a bank of 40 resettable slide switches. of each directly affect productivity.A four-station system, for example,may or may not be able to distribute its General considerations in services among three probe stations and one final test the evaluation of Ic test equipment station,or among four stations testing four different The first requirement of any testing,productivity con- devices,or among three classification stations and one siderations notwithstanding,is that the tests be valid. data-logging station. In IC testing this means (1)identifying those parameters 3.Handling speed.If devices are manually inserted into that adequately define the“goodness'"or“badness'”ofa a test socket of a single-station system,the operator's device,(2)ensuring that the conditions of measurement handling rate will almost certainly be the major factor relate meaningfully to the conditions of use,and (3) limiting throughput.It is the great imbalance between achieving the desired accuracy of measurement. testing and handling speeds,in fact,that provides the Specifying the accuracy of IC measurements is an rationale for multiplexing. especially precarious business because the test environ- The use of automatic handling equipment speeds up ment is unpredictable-and often hostile.Extremely high the mechanical end of the process to the point where accuracy and precision are rarely primary considerations, several thousand devices an hour can be tested at a single since the required levels are usually well within the state station,assuming that the test sequence per device is fairly of the art.Instead,the emphasis is on repeatability,with simple. periodic verification of accuracy.The word"calibration" The fastest mechanical handler cannot begin to match is anathema to most test-system users,because it implies the test system's speed for simple devices (e.g.,well under downtime.When a system is found to be outside toler- 100 ms to test a gate).Where automatic handlers are ance one approach is isolation and quick replacement of to be multiplexed,however,test time and handling the guilty component. converge,and the relation between the two must be Although accuracy and precision-in the traditional noted in setting up the test installation and program. instrument sense-are not primary issues,the "analog" 4.Programming and debugging.A computer-operated performance of an IC test system most certainly is.A test system is normally supplied with an executive pro- "clean"transition,without overshoot or ringing,is es- gram that contains the formatting and subroutines needed sential if fast devices are to be exercised without ambi- for a given type of application (end-of-life testing,classi- guity.The signal should be clean at the device under fication,etc.).The user must write and enter his own test,which in production testing usually means at a test specifications (bias conditions,limits,bin criterions, prober or handler separated from the signal source by a etc.),and then he must verify and correct ("debug")his length of cable. program as necessary.The debugging procedure can easily consume great amounts of time (an hour a day is Productivity not at all unusual),so a test system must be evaluated in Since economics are such a dominant factor in semicon- the light of its ability to time-share programming and ductor production,one tends to think not of the cost of a debugging with normal testing and the availability of tester but of the cost of testing.Thus productivity is a debugging aids (panel indicators,check-sum verifica- much-used term and a much-sought-after characteristic tion of software,etc.). of test equipment.Productivity in testing is a function of 5.Downtime.Downtime is the total time during which many variables,including the following: a test system is not available for normal testing.In any 1.Test speed.Although speed is the most obvious calculation of productivity,downtime obviously comes factor,it is rarely the most important.Even the slowest right "off the top,"all other factors coming into play test system is so fast that the real productivity limitations only when the system is operative.It is a difficult param- arise elsewhere. eter to quantify when making a purchasing decision,but 2.Multiplex capability.Many test systems provide for it is so important that an effort must be made.Consider some degree of multiplexing,or the simultaneous use of the difference in productivity between a test system regu- two or more test stations with a single test system larly experiencing 20 percent downtime (a not unusual figure)and one with 1 percent downtime (also a not unusual figure). 6.Retest load.If a system is not testing devices properly, FIGURE 6.An incoming-inspection instrument for linear the lots rejected by quality assurance (QA)or incoming ICs (the General Radio 1730 Linear Circuit Tester). inspection will usually find their way back to be tested again.A system that is out of calibration will therefore directly penalize system productivity. 7.Test-plan efficiency.In most cases,the number of tests required to test an IC adequately is not subject to rigid definition.One can determine easily enough the number of truth-table combinations for a simple IC,but where this number becomes overwhelmingly large,atten- tion shifts to the number required for adequate (rather than exhaustive)testing,leaving room for wide system-to- system variations.Judgment dictates the proper extent of dc parametric or linear testing per device,but system flexibility converts this judgment into productivity.If the testing objective is usually to characterize an IC as IEEE spectrum DECEMBER 1971

6. This instrument is programmed by a plug-in card The number of stations and the level of independence containing a bank of 40 resettable slide switches. of each directly affect productivity. A four-station system, for example, may or may not be able to distribute its General considerations in services among three probe stations and one final test the evaluation of IC test equipment station, or among four stations testing four different The first requirement of any testing, productivity con- devices, or among three classification stations and one siderations notwithstanding, is that the tests be valid. data-logging station. In IC testing this means (1) identifying those parameters 3. Handling speed. If devices are manually inserted into that adequately define the "goodness" or "badness" of a a test socket of a single-station system, the operator's device, (2) ensuring that the conditions of measurement handling rate will almost certainly be the major factor relate meaningfully to the conditions of use, and (3) limiting throughput. It is the great imbalance between achieving the desired accuracy ofmeasurement. testing and handling speeds, in fact, that provides the Specifying the accuracy of IC measurements is an rationale for multiplexing. especially precarious business because the test environ- The use of automatic handling equipment speeds up ment is unpredictable-and often hostile. Extremely high the mechanical end of the process to the point where accuracy and precision are rarely primary considerations, several thousand devices an hour can be tested at a single since the required levels are usually well within the state station, assuming that the test sequence per device is fairly of the art. Instead, the emphasis is on repeatability, with simple. periodic verification of accuracy. The word "calibration" The fastest mechanical handler cannot begin to match is anathema to most test-system users, because it implies the test system's speed for simple devices (e.g., well under downtime. When a system is found to be outside toler- 100 ms to test a gate). Where automatic handlers are ance one approach is isolation and quick replacement of to be multiplexed, however, test time and handling the guilty component. converge, and the relation between the two must be Although accuracy and precision-in the traditional noted in setting up the test installation and program. instrument sense-are not primary issues, the "analog" 4. Programming and debugging. A computer-operated performance of an IC test system most certainly is. A test system is normally supplied with an executive pro- "clean" transition, without overshoot or ringing, is es- gram that contains the formatting and subroutines needed sential if fast devices are to be exercised without ambi- for a given type of application (end-of-life testing, classi￾guity. The signal should be clean at the device under fication, etc.). The user must write and enter his own test, which in production testing usually means at a test specifications (bias conditions, limits, bin criterions, prober or handler separated from the signal source by a etc.), and then he must verify and correct ("debug") his length of cable. program as necessary. The debugging procedure can easily consume great amounts of time (an hour a day is Productivity not at all unusual), so a test system must be evaluated in Since economics are such a dominant factor in semicon- the light of its ability to time-share programming and ductor production, one tends to think not of the cost of a debugging with normal testing and the availability of tester but of the cost of testing. Thus productivity is a debugging aids (panel indicators, check-sum verifica￾much-used term and a much-sought-after characteristic tion of software, etc.). of test equipment. Productivity in testing is a function of 5. Downtime. Downtime is the total time during which many variables, including the following: a test system is not available for normal testing. In any 1. Test speed. Although speed is the most obvious calculation of productivity, downtime obviously comes factor, it is rarely the most important. Even the slowest right "off the top," all other factors coming into play test system is so fast that the real productivity limitations only when the system is operative. It is a difficult param￾arise elsewhere. eter to quantify when making a purchasing decision, but 2. Multiplex capability. Many test systems provide for it is so important that an effort must be made. Consider some degree of multiplexing, or the simultaneous use of the difference in productivity between a test system regu￾two or more test stations with a single test system. larly experiencing 20 percent downtime (a not unusual figure) and one with 1 percent downtime (also a not unusual figure). 6. Retest load. If a system is not testing devices properly, the lots rejected by quality assurance (QA) or incoming FIGURE 6. An incoming-inspection instrument for linear inspection will usually find their way back to be tested teGeea aio13 iea ii Testeagain. A system that is out of calibration will therefore ~~~~~~~ ~~~~~~directly penalize system productivity. 7. Test-plan efficiency. In most cases, the number of tests required to test an IC adequately is not subject to rigid definition. One can determine easily enough the number of truth-table combinations for a simple IC, but where this number becomes overwhelmingly large, atten￾tion shifts to the number required for adequate (rather than exhaustive) testing, leaving room for wide system-to￾system variations. Judgment dictates the proper extent of dc parametric or linear testing per device, but system fiexibility converts this judgmnent into productivity. If the testing objective is usually to characterize an IC as 34 ~~~~~~~~~~~~~~~~~~~~~~~~~~IEEE spectrUM DECEMBER 1971

“good'or“bad,”then it is not enough to reduce the test systems are helped greatly in their battle against ob- total number of tests needed from,say,50 to 40 per device. solescence by the fact that many of them are computer- Why bother making 40 tests on a bad device?Why not controlled.Give a computerized system a new software arrange the order of tests so that bad devices are dis- package and it is effectively a new system.(For this qualified as soon as possible-perhaps even after one or reason,if for no other,the computer-operated system two tests?This suggests placing the most critical tests represents more actual value than a hard-wired or tape- first in the sequence (e.g.,testing for catastrophic failures. programmed system.)For all its newly acquired intelli- then functionally testing,then parametrically);but there is gence,however,the older system is not likely to be as more to it than that.If a given test,no matter how productive as newer systems,so its versatility can take critical,is almost always passed,then it is a waste of it only so far. time to put it at the head of the sequence.The possibilities are seen to be endless in theory,but in practice they System compatibility are limited by the flexibility of the test-system hardware Although some bench-top IC testers operate "bare- and software. foot"in incoming inspection facilities,IC testing is by 8.Data logging.Although the concept of productivity and large a systems operation,and the typical IC test in semiconductor testing usually refers to device through- system finds itself surrounded by wafer probers,ovens, put,it is also validly applied to the rate of generation of automatic handlers,scanners,recorders,and other han- test data(summary sheets,distribution analyses,end-of- dling and processing paraphernalia.Thus the designer of life data,etc.).The speed of the data-logging medium an IC test system must take into account the fact that a (teleprinter,line printer,etc.)is important,though less so wafer prober will introduce probe capacitance,that long than one might think:Much data logging is quickly stored leads will be required to connect to automatic handlers, on magnetic tape for later,off-line printout. that the user may want to add auxiliary instruments to the The foregoing considerations apply chiefly to large setup,etc. test systems in production applications and to a lesser It is reasonable to expect the maker,rather than the degree to IC test instruments used in inspection or engi- buyer,of an IC test system to assume most of the inter- neering.A production test system,remember,is as much face worries.The vagaries of automatic handlers and a part of the manufacturing process as a diffusion furnace. probers are well known to any established producer of Since no one is really happy with a manufacturing facility IC test equipment,and it makes little sense for a system operating below capacity,the ideal condition is one in buyer to learn them the hard way. which the test equipment,along with everything else,is being pushed to its limit.In most inspection operations, Easy programming on the other hand,test equipment is purchased not The phrase "easy programming"has been applied because a plant would cease to function without it but to every commercial test system,to the point of meaning- in order to reduce costs of equipment rework and service. An inspection instrument can be idle half the time and still easily earn its keep.This is not to suggest that those who manage inspection facilities are not concerned with productivity;they are,but they define productivity in FIGURE 7.Magnetic-tape cartridge carries test program broader terms,including the total time spent on the end and "device board"houses output loads and other spec- product. ialized test hardware for use with Teradyne J277 MOS Test System,in background. Versatility and obsolescence Any realistic appraisal of IC technology would have to conclude that,far from being a mature field,it has yet to approach full development.The 300 million ICs produced in 1970 include hardly any for consumer and automotive electronics,two areas of major potential.(It has been estimated that the automotive industry alone could con- sume 200 million ICs annually by 1974.)New applica- tions breed basic device changes.So does the current heavy expenditure in semiconductor R&D.Variations on the MOS theme seem to occur weekly.All of this seems to threaten all existing IC test equipment with early obsolescence. Yet most of the several hundred production test systems shipped during 1967 and 1968 are still hard at work for their owners.How can a system designed for 1967 IC technology handle 1971 devices?The answer lies in the fact that the technological ground rules for IC testing have been fairly well established for years.New types of devices require new testing technology,to be sure,but a gate today is tested very much the same way a gate was tested several years ago.The advances have come in the number of gates that can be tested per unit time and in overall system performance parameters.Yesterday's IC Van Veen-An introduction to IC testing 35

"good" or "bad," then it is not enough to reduce the test systems are helped greatly in their battle against ob￾total number oftests needed from, say, 50 to 40 per device. solescence by the fact that many of them are computer￾Why bother making 40 tests on a bad device? Why not controlled. Give a computerized system a new software arrange the order of tests so that bad devices are dis- package and it is effectively a new system. (For this qualified as soon as possible-perhaps even after one or reason, if for no other, the computer-operated system two tests? This suggests placing the most critical tests represents more actual value than a hard-wired or tape￾first in the sequence (e.g., testing for catastrophic failures, programmed system.) For all its newly acquired intelli￾then functionally testing, then parametrically); but there is gence, however, the older system is not likely to be as more to it than that. If a given test, no matter how productive as newer systems, so its versatility can take critical, is almost always passed, then it is a waste of it only so far. time to put it at the head of the sequence. The possibilities are seen to be endless in theory, but in practice they System compatibility are limited by the flexibility of the test-system hardware Although some bench-top IC testers operate "bare￾and software. foot" in incoming inspection facilities, IC testing is by 8. Data logging. Although the concept of productivity and large a systems operation, and the typical IC test in semiconductor testing usually refers to device through- system finds itself surrounded by wafer probers, ovens, put, it is also validly applied to the rate of generation of automatic handlers, scanners, recorders, and other han￾test data (summary sheets, distribution analyses, end-of- dling and processing paraphernalia. Thus the designer of life data, etc.). The speed of the data-logging medium an IC test system must take into account the fact that a (teleprinter, line printer, etc.) is important, though less so wafer prober will introduce probe capacitance, that long than one might think: Much data logging is quickly stored leads will be required to connect to automatic handlers, on magnetic tape for later, off-line printout. that the user may want to add auxiliary instruments to the The foregoing considerations apply chiefly to large setup, etc. test systems in production applications and to a lesser It is reasonable to expect the maker, rather than the degree to IC test instruments used in inspection or engi- buyer, of an IC test system to assume most of the inter￾neering. A production test system, remember, is as much face worries. The vagaries of automatic handlers and a part of the manufacturing process as a diffusion furnace. probers are well known to any established producer of Since no one is really happy with a manufacturing facility IC test equipment, and it makes little sense for a system operating below capacity, the ideal condition is one in buyer to learn them the hard way. which the test equipment, along with everything else, is being pushed to its limit. In most inspection operations, Easy programming on the other hand, test equipment is purchased not The phrase "easy programming" has been applied because a plant would cease to function without it but to every commercial test system, to the point of meaning￾in order to reduce costs of equipment rework and service. An inspection instrument can be idle half the time and still easily earn its keep. This is not to suggest that those who manage inspection facilities are not concerned with productivity; they are, but they define productivity in FIGURE 7. Magnetic-tape cartridge carries test program broader terms, including the total time spent on the end and "device board" houses output loads and other spec￾product. ialized test hardware for use with Teradyne J277 KOS Test System, in background. Versatility and obsolescence Any realistic appraisal of IC technology would have to conclude that, far from being a mature field, it has yet to .l. approach full development. The 300 million ICs produced * in 1970 include hardly any for consumer and automotive -i* electronics, two areas of major potential. (It has been estimated that the automotive industry alone could con￾sume 200 munllon ICs annually by 1974.) New applica￾tions breed basic device changes. So does the current heavy expenditure in semiconductor R&D. Variations on the MOS theme seem to occur weekly. All of this seems to threaten all existing IC test equipment with early obsolescence. Yet most ofthe several hundred production test systems shipped during 1967 and 1968 are stiUl hard at work for their owners. How can a system designed for 1967 IC technology handle 1971 devices? The answer lies in the fact that the technological ground rules for IC testing have been fairly well established for years. New types of devices require new testing technology, to be sure, but a gate today is tested very much the same way a gate was tested several years ago. The advances have come in the number of gates that can be tested per unit time and in overall system performance parameters. Yesterday's IC Van Veen-An introduction to IC testing 35

lessness.In fact,writing the program (once one decides example,the programming of a pulse parametric test what he wants to test)is a fairly simple matter with any on Teradyne's J277 MOS Test System;see Fig.7. system.A language and some syntax must be learned, To set up the timing of clocks and output strobe the but the learning generally requires only a day or two,and operator might write: sometimes much less.One is ill-advised to select a test CLOCK 1 system because it is easier to write programs for it than 100 NS FROM TO for another system.In fact,the easier language may re- GAP1 70 NS FROM CLOCK 1 flect a more limited testing capability.The most effective CLOCK 2 210 NS FROM GAP 1 utilization of a test system normally results when a good STROBE 1 300 NS FROM TO technician,having learned all the nuances of an extensice (In this example a gap is defined to indicate that the system language,calls into play all the testing power at clocks do not overlap.)The operator commands the his command system to measure the leakage current on pin 2,rejecting The concept of easy programming is more valid,how- anything more negative than -500 mA at -18 volts, ever,when applied to the type(rather than the size)of as follows: a programming language.Languages are sometimes characterized as "high level"or "low level."A high- MCON PIN 2 level language is designed exclusively for the testing job MEASURE -500 MA AT -18V;RNEG at hand,whereas a low-level language is for general- Not all test-system languages are as close to plain English purpose use.A high-level language geared to IC-testing as the foregoing,but many use mnemonics that are easily terminology obviously will be easier to program in that mastered. application than a low-level language.Consider.for Sizing the equipment to the job Most of the points discussed so far relate chiefly to the use of IC test systems.The world of IC testing,however, embraces bench-top IC testers as well as large,produc- FIGURE 8.Two computer-operated test systems.(Top) Teradyne J283/Si57 system for functional,dc,and pulse tion-oriented systems.In some ways the smaller instru- parametric testing.(Bottom)Datatron 4400 for functional ments are the equal of their massive counterparts.A and dc parametric testing. bench-top tester may well be able to perform functional tests on a given IC as fast as any large system can.Small testers are in fact sometimes interfaced to systems,in order to screen out functional failures as fast as possible, before proceeding to parametric testing. At the low end of the price spectrum of IC test equip- ment is the manually programmed tester costing a few hundred dollars.It can functionally check a simple IC and that is about all.It is useless for the testing of ICs in any volume. A fairly large selection of equipment is available in the $3000-$8000 range.Instruments in this class are typically comparison testers,programmed by plug-in printed- circuit cards,with a binary generator handling the func- tional-testing requirements at very respectable speeds. Instruments of this type are not to be taken lightly. Interfaced to an automatic handler,a $5000 IC tester can throw several thousand ICs an hour into "good" and "bad"bins,on the basis of both functional and parametric test results. In determining whether or not a bench-top instrument will satisfy one's testing needs,the best approach is prob- ably to examine the things that such an instrument cannot do,then determine whether any of these are crucial in a given application.Specifically,and with very few excep- tions,the bench-top tester cannor generate test data; match the multiplexing ability of a large system;provide for dynamic testing;handle as many different types of IC as a computerized system can;perform thorough func- tional testing of devices having sequential logic;make highly accurate and precise parametric tests;or make burn-in or life tests. These limitations rule out the bench-top tester for production and QA testing and incoming inspection where test data are required.Once it is determined that the bench-top tester is inadequate for the job at hand, the next step up the performance scale is the S50000- and-up computer-operated test system.(An exception is IEEE spectrum DECEMBER 1971

lessness. In fact, writing the program (once one decides example, the programming of a pulse parametric test what he wants to test) is a fairly simple matter with any on Teradyne's J277 MOS Test System; see Fig. 7. system. A language and some syntax must be learned, To set up the timing of clocks and output strobe the but the learning generally requires only a day or two, and operator might write: sometimes much less. One is ill-advised to select a test CLOCK I 100 NS FROM TO system because it is easier to write programs for it than GAP 1 70 NS FROM CLOCK I for another system. In fact, the easier language may re- CLOCK 2 210 NS FROM GAP I flect a more limited testing capability. The most effective STROBEI 300 NS FROM TO utilization of a test system normally results when a good technician, having learned all the nuances of an extensive (In this example a gap is defined to indicate that the system language, calls into play all the testing power at clocks do not overlap.) The operator commands the his command. system to measure the leakage current on pin 2, rejecting The concept of easy programming is more valid, how- anything more negative than -500 mA at -18 volts, ever, when applied to the type (rather than the size) of as follows: a programming language. Languages are sometimes characterized as "high level" or "low level." A high- MCON PIN 2 level language is designed exclusively for the testing job MEASURE-500 MA AT-18V; RNEG at hand, whereas a low-level language is for general- Not all test-system languages are as close to plain English purpose use. A high-level language geared to IC-testing as the foregoing, but many use mnemonics that are easily terminology obviously will be easier to program in that mastered. application than a low-level language. Consider, for Sizing the equipment to the job Most of the points discussed so far relate chiefly to the use of IC test systems. The world of IC testing, however, embraces bench-top IC testers as well as large, produc- FIGURE 8. Two computer-operated test systems. (Top) tion-oriented systems. In some ways the smaller instru￾Teradyne J283/Si57 system for functional, dc, and pulse parametrictesting. (Bottom)Datatron4400forfunctional ments are the equal of their massive counterparts. A and dc parametric testing. bench-top tester may well be able to perform functional tests on a given IC as fast as any large system can. Small testers are in fact sometimes interfaced to systems, in order to screen out functional failures as fast as possible, before proceeding to parametric testing. At the low end of the price spectrum of IC test equip￾ment is the manually programmed tester costing a few hundred dollars. It can functionally check a simple IC, and that is about all. It is useless for the testing of ICs in any volume. A fairly large selection of equipment is available in the $3000-$8000 range. Instruments in this clas are typically comparison testers, programmed by plug-in printed￾circuit cards, with a binary generator handling the func￾tional-testing requirements at very respectable speeds. Instruments of this type are not to be taken lightly. Interfaced to an automatic handler, a $5000 IC tester can throw several thousand ICs an hour into "good" and "bad" bins, on the basis of both functional and parametric test results. .36 In determining whether or not a bench-top instrument . .,, ~~~~will satisfy one's testing needs, the best approach is prob￾ably to examine the things that such an instrument cannot do, then determine whether any of these are crucial in a given application. Specifically, and with very few excep￾tions, the bench-top tester cannot generate test data; match the multiplexing ability of a large system; provide for dynamic testing; handle as many different types of IC as a computerized system can; perform thorough func￾tional testing of devices having sequential logic; make highly accurate and precise parametric tests; or make burn-in or life tests. These limitations rule out the bench-top tester for production and QA testing and incoming inspection ~~~~~~~~ ~~~~~~~where test data are required. Once it is determiined that the bench-top tester is inadequate for the job at hand, the next step up the performiance scale is the $50000- and-up computer-operated test system. (An excepition is 36 MEEE spectrum DEcEmBER 1971

the noncomputer-operated memory tester at $15 000- Redcor Corp.,21200 Victory Blvd.,Woodland Hills, $20000.)A fully equipped,computer-operated dc test Calif.91364 (computer-operated MOS test systems) system for bipolar devices can be purchased for well under Tektronix,Inc.,P.O.Box 500,Beaverton,Oreg.97005 $100 000.Addition of a dynamic testing capability raises (computer-operated MOS and bipolar test systems) the price to the $100000 to $150 000 range.Computer- Teradyne,Inc.,183 Essex St.,Boston,Mass.02111 ized systems for the clock-rate testing of MOS begin at (computer-operated MOS,bipolar,and linear test about $100 000.Two representative computer-operated systems;digital test instruments) test systems are shown in Fig.8. Teradyne Dynamic Systems,9551 Irondale Ave.,Chats- Support costs for an Ic test system-the costs of worth,Calif.91311 (computer-operated bipolar test maintenance,calibration,programming,special test systems) fixturing,etc.-vary widely,in many cases exceeding the Watkins-Johnson,Inc.,3333 Hillview Ave.,Palo Alto, initial system cost within the first year of operation. Calif.94304 (computer-operated bipolar test systems) There are many ways of minimizing such support costs, Western Digital,1612 S.Lynn St.,Santa Ana,Calif. and most of them bear on the selection of the test system. 92705 (computer-operated bipolar and MOS test The desire to reduce programming,debugging,and ser- systems) vice costs explains the banks of indicator lamps on the Xintel Corp.,20931 Nordhoff St.,Chatsworth,Calif. front panels of some test systems.These lamps are of 91311 (computer-operated bipolar and MOS test sys- no use during normal operation but are indispensable tems) in setting up and checking the system. BIBLIOGRAPHY Conclusion Attridge,W.A.. “Caution:test op amps carefully,”Electron.. The field of IC testing has been a showcase for com Design,Nov.8,1969. puter control and automation.Much of the system "Automatic and manual integrated circuit test equipment,"SETE expertise that has been developed is applicable to 210/96,Project SETE,New York University,Aug.1968. electronics production in general.This implies great Beck,R.,"Functional-testing an IC memory,"Application Rept. 105,Teradyne,Inc. opportunities for increased productivity in our industry Bourne,R.B.,Jr.,"Fault detection in bipolar integrated circuit which is,curiously,one of the least automated of all. outputs,"Application Rept.113,Teradyne,Inc. Boyle,A.J.,"Testing MOS,"Electron.Engr.,Oct.1970. Appendix:Manufacturers of Ic test equipment Curran,L.. "Meeting the MOS/LSI challenge:a special report on testers,"Electronics,May 10,1971. IC test equipment is commercially produced by about Edelman,S.,"Testing integrated circuits,"Electron.Engr..Sept two dozen firms.New developments come so fast in this 1970. field that it would be neither helpful to the reader nor Egan,F.,and Speer,R.,eds.,"IC testing-a special report," Electron.Design,Sept.1,1968. fair to the manufacturers to attempt to list equipment Flynn,G.,"Forum on op amps,"Electron.Products,Dec.1968. specifications.Names and addresses of the major manu- Padwick,G.B.."Dynamic IC testing made easy,"Electronics, facturers are given below for the benefit of those interested Scpt.30.1968. in obtaining information on the characteristics and Salvador,J.,"Today's dynamic IC tests won't work without application of IC test equipment. meaningful specs,"Electronics,Nov.8,1971. Adar Associates,Inc.,85 Bolton St.,Cambridge,Mass. Seaton,J.,"Testing low input currents in operational amplifiers," Application Rept.106,Teradyne,Inc. 02140 (computer-operated bipolar and MOS test Young,F.M.,"Clock-rate testing in a realistic environment," systems) 1971 WESCON Rec. Alma Corp.,570 Del Rey Ave.,Sunnyvale,Calif.94086 (digital IC test instruments) Datatron,Inc.,1562 Reynolds Ave.,Santa Ana,Calif. Reprints of this article (No.X71-122)are available to 92711 (computer-operated bipolar and MOS test readers.Please use the order form on page 8,which gives information and prices. systems) E-H Research Laboratories,Inc.,515 11th St.,Oakland, Calif.94604 (computer-operated bipolar and MOS test systems) Frederick Van Veen (SM) Fairchild Systems Technology,974 E.Arques Ave., received the B.A.degree Sunnyvale,Calif.94086 (computer-operated MOS, from Boston College in bipolar,and linear test systems;linear IC test instru- 1951.After graduation he served as an officer in the ments) U.S.Army Reserve,com- General Radio Co.,300 Baker Ave.,Concord,Mass. pleting various courses in 07142 (linear test instruments) electronics at the Artillery LSI Testing,Inc.,2280 S.Main St.,Salt Lake City,Utah School,Fort Bliss,Tex 84115 (computer-operated bipolar and MOS test He joined the General Radio Company in 1955; systems) later he became publicity Macrodata,Inc.,20440 Corisco St.,Chatsworth,Calif. manager and editor of the 91311 (computer-operated MOS and bipolar test General Radio Experimenter.In 1968 he joined Teradyne,Inc.,where he is now director of corporate systems;memory test instruments) relations.He has written extensively on the subjects Microdyne Instruments,Inc.,203 Middlesex Turnpike, of electronic instrumentation and semiconductor Burlington,Mass.01803 (digital and linear test testing.Since 1965 he has served as editor of the instruments) IEEE Transactions on Audio and Electroacoustics Optimized Devices,220 Marble Ave.,Pleasantville, He is also past national chairman of the IEEE N.Y.10570 (linear test systems) Engineering Writing and Speech Group. Van Veen-An introduction to IC testing 37

the noncomputer-operated memory tester at $15 000- Redcor Corp., 21200 Victory Blvd., Woodland Hills, $20000.) A fuUy equipped, computer-operated dc test Calif. 91364 (computer-operated MOS test systems) system for bipolar devices can be purchased for well under Tektronix, Inc., P.O. Box 500, Beaverton, Oreg. 97005 $100 000. Addition of a dynamic testing capability raises (computer-operated MOS and bipolar test systems) the price to the $100 000 to $150 000 range. Computer- Teradyne, Inc., 183 Essex St., Boston, Mass. 02111 ized systems for the clock-rate testing of MOS begin at (computer-operated MOS, bipolar, and linear test about $100 000. Two representative computer-operated systems; digital test instruments) test systems are shown in Fig. 8. Teradyne Dynamic Systems, 9551 Irondale Ave., Chats￾Support costs for an IC test system-the costs of worth, Calif. 91311 (computer-operated bipolar test maintenance, calibration, programming, special test systems) fixturing, etc.-vary widely, in many cases exceeding the Watkins-Johnson, Inc., 3333 Hillview Ave., Palo Alto, initial system cost within the first year of operation. Calif. 94304 (computer-operated bipolar test systems) There are many ways of minimizing such support costs, Western Digital, 1612 S. Lynn St., Santa Ana, Calif. and most of them bear on the selection of the test system. 92705 (computer-operated bipolar and MOS test The desire to reduce programming, debugging, and ser- systems) vice costs explains the banks of indicator lamps on the Xintel Corp., 20931 Nordhoff St., Chatsworth, Calif. front panels of some test systems. These lamps are of 91311 (computer-operated bipolar and MOS test sys￾no use during normal operation but are indispensable tems) in setting up and checking the system. BIBLIOGRAPHY Conclusion Attridge, W. A., "Caution: test op amps carefully," Electron. The field of IC testing has been a showcase for com- Design, Nov. 8, 1969. puter control puter and automation. Much of the system "Automatic and manual integrated circuit test equipment," SETE ~~~~~~~~~~~~~~210/96, Project SETE, New York University, Aug. 1968. expertise that has been developed is applicable to Beck, R., "Functional-testing an IC memory," Application Rept. electronics production in general. This implies great 105, Teradyne, Inc. opportunities for increased productivity in our industry, Bourne, R. B., Jr., "Fault detection in bipolar integrated circuit which is, curiously, one of the least automated of all. outputs," Application Rept. 113, Teradyne, Inc. Boyle, A. J., "Testing MOS," Electron. Engr., Oct. 1970. Appendix: Manufacturers Manufactrers ofofCIC test test equipment euipment Curran, L., "Meeting the MOS/LSI challenge: a special report on testers," Electronics, May 10, 1971. IC test equipment is commercially produced by about Edelman, S., "Testing integrated circuits," Electron. Engr., Sept two dozen firms. New developments come so fast in this 1970. field that it would be neither helpful to the reader nor Egan, F., and Speer, R., eds., "IC testing-a special report," Electron. Design, Sept. 1, 1968. fair to the manufacturers to attempt to list equipment Flynn, G., "Forum on op amps," Electron. Products, Dec. 1968. specifications. Names and addresses of the major manu- Padwick, G. B,, "Dynamic IC testing made easy," Electronics. facturers are given below for the benefit of those interested Sept. 30, 1968. in obtaining information on the characteristics and Salvador, J., "Today's dynamic IC tests won't work without application of IC test equipment. meaningful specs," Electronics, Nov. 8, 1971. Seaton, J., "Testing low input currents in operational amplifiers," Adar Associates, Inc., 85 Bolton St., Cambridge, Mass. Application Rept. 106, Teradyne, Inc. 02140 (computer-operated bipolar and MOS test Young, F. M., "Clock-rate testing in a realistic environment," systems) 1971 WESCON Rec. Alma Corp., 570 Del Rey Ave., Sunnyvale, Calif. 94086 (digital IC test instruments) Datatron, Inc., 1562 Reynolds Ave., Santa Ana, Calif. Reprints of this article (No. X71.122) are available to 92711 (computer-operated bipolar and MOS test readsrsfPiease use the order form on pago , which systems) E-H Research Laboratories, Inc., 515 11th St., Oakland, Calif. 94604 (computer-operated bipolar and MOS test systems) Frederick Van Veen (SM) Fairchild Systems Technology, 974 E. Arques Ave., received the B.A. degree Sunnyvale, Calif. 94086 (computer-operated MOS, from Boston College in and linear test systems; linear IContest;instru- . e1951. After graduation he bipolar, and Mserved as an officer in the ments) U.S. Army Reserve, com￾General Radio Co., 300 Baker Ave., Concord, Mass. pleting various courses in 07142 (linear test instruments) electronics at the Artillery LSI Testing, Inc., 2280 S. Main St., Salt Lake City, Utah School, Fort Bliss, Tex. He joined the General 84115 (computer-operated bipolar and MOS test Radio Company in 1955; systems) later he became publicity Macrodata, Inc., 20440 Corisco St., Chatsworth, Calif. manager and editor ofthe 91311 (computer-operated MOS and bipolar test General Radio Experimenter. In 1968 he joined memory test instruments) ~~Teradyne, Inc., where he is now director of corporate systems; memory test instru,ents) relations. He has written extensively on the subjects Microdyne Instruments, Inc., 203 Middlesex Turnpike, of electronic instrumentation and semiconductor Burlington, Mass. 01803 (digital and linear test testing. Since 1965 he has served as editor of the instruments) IEEE Transactions on Audio and Electroacoustics. Optimized Devices, 220 Marble Ave., Pleasantville, He is also past national chairman of the IEEE N.Y. 10570 (linearic es,t220 Marblems) Av. laatil, Engineering Writing and Speech Group. N.Y. 10570 (linearotest systems) 37 Van Veen-An introduction to IC testing