Part VI Extend your multiplier to multiply 8-bit numbersand produce a 16-bit product.Use switches SW to represent the numbe 4y the X B n fo the registered adder in Figure 1. After successfully compiling and testing your multiplier circuit,examine the results produced by the Quartus Anayer to the ax ofyour cirut What is th path in of delay beeen Part VII Change your VHDL code to implemen module from th ofthe numroem(LE)nedeand the ciruit Part VIll It many applications of digital circuits it is useful to be able to perform some number of multiplications and then produce a summation of the results.For this part of the exercise you are to design a circuit that performs the calculation S=(A×B)+(C×D) The inputs A.B.C.and D are eight-bit unsig ned numbers.and S provides a 16-bit result.Your circuit should also provide a carry-out signal,All of the inputs and outputs of the circuit should be registered,similar to the structure shown in Figure 1b 1.Create a new Quartus lI project which will be used to implement the desired circuit on the Altera DE2 board Use the Ipmmult and Ipm_add_sub modules to realize the multipliers and adders in your design. nd C to witches SW5- s and cor es SW7-0.Use wEo动oda inpata to be aded in when an act clock edge occurs.while setting WEtoshould prevent loading of these registers. 3.Use KEYo as an active-low asynchronous reset input,and use KEY as a manual clock input 4BziEsncn 6.It is often articular mec th in the form ofmnconsThe procedure for using timing constraints in the Quartus IICAD system is described in the tutorial Timing Considerationswith VHDL-Based Designs,which is available on the DE2 System CD and in the University Program section of Altera's web site. For this exercise we are using a manual clock that is applied by a pushbutton switch,so no realistic timing requirements ex But to demon s involved,assume that your circuit is required to The Tim due tothelengtofariousesterto-register paths in the circuit Examine the tmn analysis report and describe briefly the timing violations observed. Part VI Extend your multiplier to multiply 8-bit numbers and produce a 16-bit product. Use switches SW 15−8 to represent the number A and switches SW7−0 to represent B. The hexadecimal values of A and B are to be displayed on the 7-segment displays HEX7−6 and HEX5−4, respectively. The result P = A × B is to be displayed on HEX3−0. Add registers to your circuit to store the values of A, B, and the product P, using a similar structure as shown for the registered adder in Figure 1. After successfully compiling and testing your multiplier circuit, examine the results produced by the Quartus II Timing Analyzer to determine the fmax of your circuit. What is the longest path in terms of delay between registers? Part VII Change your VHDL code to implement the 8 x 8 multiplier by using the lpm mult module from the library of parameterized modules in the Quartus II system. Complete the design steps above. Compare the results in terms of the number of logic elements (LEs) needed and the circuit fmax. Part VIII It many applications of digital circuits it is useful to be able to perform some number of multiplications and then produce a summation of the results. For this part of the exercise you are to design a circuit that performs the calculation S = (A × B)+(C × D) The inputs A, B, C, and D are eight-bit unsigned numbers, and S provides a 16-bit result. Your circuit should also provide a carry-out signal, Cout. All of the inputs and outputs of the circuit should be registered, similar to the structure shown in Figure 1b. 1. Create a new Quartus II project which will be used to implement the desired circuit on the Altera DE2 board. Use the lpm mult and lpm add sub modules to realize the multipliers and adders in your design. 2. Connect the inputs A and C to switches SW15−8 and connect the inputs B and D to switches SW7−0. Use switch SW16 to select between these two sets of inputs: A, B or C, D. Also, use the switch SW17 as a write enable (WE) input. Setting WE to 1 should allow data to be loaded into the input registers when an active clock edge occurs, while setting WE to 0 should prevent loading of these registers. 3. Use KEY0 as an active-low asynchronous reset input, and use KEY 1 as a manual clock input. 4. Display the hexadecimal value of either A or C, as selected by SW16, on displays HEX7-6 and display either B or D on HEX5-4. The sum S should be shown on HEX3-0, and the C out signal should appear on LEDG8. 5. Compile your code and use either functional or timing simulation to verify that your circuit works properly. Then download the circuit onto the DE2 board and test its operation. 6. It is often necessary to ensure that a digital circuit is able to meet certain speed requirements, such as a particular frequency of a signal applied to a clock input. Such requirements are provided to a CAD system in the form of timing constraints. The procedure for using timing constraints in the Quartus II CAD system is described in the tutorial Timing Considerations with VHDL-Based Designs, which is available on the DE2 System CD and in the University Program section of Altera’s web site. For this exercise we are using a manual clock that is applied by a pushbutton switch, so no realistic timing requirements exist. But to demonstrate the design issues involved, assume that your circuit is required to operate with a clock frequency of 220 MHz. Enter this frequency as a timing constraint in the Quartus II software, and recompile your project. The Timing Analyzer should report that it is unable to meet the timing requirements due to the lengths of various register-to-register paths in the circuit. Examine the timing analysis report and describe briefly the timing violations observed. 7