Laboratory Exercise 6 Adders,Subtractors,and Multipliers The purpose of this exercise is to examine arithmetic circuits that add,subtract,and multiply numbers.Each be implemented in t ways.nrst by de th describes the requr ules ared.bothin terms of the eircuit structure and its speed of operation. PartI Consider again the four-bit ripple-carry adder circuit that was used in lab exercise 2.a diagram of this circuit is ps shown below 当口学日 a)Four-bit ripple-carry adder circuit e时d b)Eight-bitregistered adder circui Figure 1.An8-bit signed adder with registered inputs and outputs
Laboratory Exercise 6 Adders, Subtractors, and Multipliers The purpose of this exercise is to examine arithmetic circuits that add, subtract, and multiply numbers. Each type of circuit will be implemented in two ways: first by writing VHDL code that describes the required functionality, and second by making use of predefined subcircuits from Altera’s library of parameterized modules (LPMs). The results produced for various implementations will be compared, both in terms of the circuit structure and its speed of operation. Part I Consider again the four-bit ripple-carry adder circuit that was used in lab exercise 2; a diagram of this circuit is reproduced in Figure 1a. You are to create an 8-bit version of the adder and include it in the circuit shown in Figure 1b. Your circuit should be designed to support signed numbers in 2’s-complement form, and the Overflow output should be set to 1 whenever the sum produced by the adder does not provide the correct signed value. Perform the steps shown below. + A S 8 8 8 B R Q R Q R Q cout cin Q D 0 Overflow Clock FA a0 b0 s0 FA c1 a1 b1 s1 FA c2 a2 b2 s2 FA c3 a3 b3 s3 cout a) Four-bit ripple-carry adder circuit cin + A S 8 8 B R Q R Q R Q Q D 0 Overflow Clock cin cout b) Eight-bit registered adder circuit Figure 1. An 8-bit signed adder with registered inputs and outputs. 1
1.Make a new Quartus lI project and write VHDL code that describes the circuit in Figure 1.Use the circuit structure in Figure atodescribe your adder. 2.Include the required input and output ports in your project to implement the adder circuit on the DE2 board. Connect the inputs A and B to switches SW1s-s and SW7.respectively.Use KEYo as an active-low s res input,and us KEY as a manual clocl input.Display the sum outputs of the adder on nal value of s should appear on HEXI-0. 3.Compile your code and use timing simulation to verify the correct operation of the circuit.Once the sim DE2 board and test it by using different values of A delay? PartⅡ and displays as described for Part I. 1.Simulate vour adder/subtractor circuit to show that it functions p roperly.and then download itonto the DE2 board and test it by using different switch settings. 2.Open the Quartus II Compilation Report and examine the results reported by the Timing Analyzer.What is the fmax of your circuit?What is the longest path in the circuit in terms of delay PartI me or n the rogram sectio of Al module in your VHDL code,compile the project and use the Quartus II Chip Editor tool to examine some of the details of the implemented circuit One way to examine the adder subcircuit using the Chip Editor tool is illustrated in Figure 2.In the Quartu right-ick the chy that ents the lpm add8 the co Thi te opens the Chip E tor windo logic element operty Editor window displayed in Figure 4.In the box labeled ws you
1. Make a new Quartus II project and write VHDL code that describes the circuit in Figure 1b. Use the circuit structure in Figure 1a to describe your adder. 2. Include the required input and output ports in your project to implement the adder circuit on the DE2 board. Connect the inputs A and B to switches SW15−8 and SW7−0, respectively. Use KEY0 as an active-low asynchronous reset input, and use KEY1 as a manual clock input. Display the sum outputs of the adder on the red LEDR7−0 lights and display the overflow output on the green LEDG8 light. The hexadecimal values of A and B should be shown on the displays HEX7-6 and HEX5-4, and the hexadecimal value of S should appear on HEX1-0. 3. Compile your code and use timing simulation to verify the correct operation of the circuit. Once the simulation works properly, download the circuit onto the DE2 board and test it by using different values of A and B. Be sure to check for proper functionality of the Overflow output. 4. Open the Quartus II Compilation Report and examine the results reported by the Timing Analyzer. What is the maximum operating frequency, fmax, of your circuit? What is the longest path in the circuit in terms of delay? Part II Modify your circuit from Part I so that it can perform both addition and subtraction of eight-bit numbers. Use switch SW16 to specify whether addition or subtraction should be performed. Connect the other switches, lights, and displays as described for Part I. 1. Simulate your adder/subtractor circuit to show that it functions properly, and then download it onto the DE2 board and test it by using different switch settings. 2. Open the Quartus II Compilation Report and examine the results reported by the Timing Analyzer. What is the fmax of your circuit? What is the longest path in the circuit in terms of delay? Part III Repeat Part I using the predefined adder circuit called lpm add sub, instead of your ripple-carry adder structure from Figure 1. The lpm add sub module can be found in Altera’s library of parameterized modules (LPMs), which is provided as part of the Quartus II system. The procedure for using these predefined modules in Quartus II projects is described in the tutorial Using Library Modules in VHDL Designs, which is available on the DE2 System CD and in the University Program section of Altera’s web site. 1. Configure the lpm add sub module so that it performs only addition, to make the functionality comparable to Part I. Store your configuration of the lpm add sub module in the file lpm add8.v. After instantiating this module in your VHDL code, compile the project and use the Quartus II Chip Editor tool to examine some of the details of the implemented circuit. One way to examine the adder subcircuit using the Chip Editor tool is illustrated in Figure 2. In the Quartus II Project Navigator window right-click on the part of your circuit hierarchy that represents the lpm add8 subcircuit, and select the command Locate > Locate in Chip Editor. This opens the Chip Editor window shown in Figure 3. The logic elements in the Cyclone II FPGA that are used to implement the adder are highlighted in blue in the Chip Editor tool. Position your mouse pointer over any of these logic elements and double-click to open the Resource Property Editor window displayed in Figure 4. In the box labeled Node name you can select any of the nine logic elements that implement the adder module. The Resource Property Editor allows you to examine the contents of a logic element and to see how one logic element is connected others. 2
Set Top-Level Entty Megawizard Plug-In Mans Figure 2.Locating the eight-bit adder in the Chip Editor tool Figure 3.The highlighted logic elements for the eight-bit adde
Figure 2. Locating the eight-bit adder in the Chip Editor tool. Figure 3. The highlighted logic elements for the eight-bit adder. 3
aon习se Figure 4.Examining details in a logic element using the Resource Property Editor. PartIV Comment briefly on the circuit structure obtained using the LPM module,and compare the fmax of this circuit to the one from Part II.Describe how the Ipmadd sub module implements the Overflow signal. g
Using the tools described above, and referencing the Data Sheet information for the Cyclone II FPGA, describe the eight-bit adder circuit implemented with the lpm add sub module. Figure 4. Examining details in a logic element using the Resource Property Editor. 2. Open the Quartus II Compilation Report and and compare the fmax of your adder circuit with the one designed in Part I. Discuss any differences in performance that are observed. Part IV Repeat Part II using the predefined adder circuit called lpm add sub, instead of your adder-subtractor circuit based on Figure 1. Comment briefly on the circuit structure obtained using the LPM module, and compare the fmax of this circuit to the one from Part II. Describe how the lpm add sub module implements the Overflow signal. 4
Part V figure shows the same example using four-bit binary numbers.Since each digit in B is either I or 0,the summand shows how each summand can be formed by using the Boolear x699 132 10000100 a)Decimal b)Binary x88&0 a3bo azbo abo aobo asby azby aby aoby a3b2 azbz abz aob2 asb3 azbs aby aoby c)Implementation Figure 5.Multiplication of binary numbers. eA ererodc hnd nd full adder ules are use to generate the required sums
Part V Figure 5a gives an example of the traditional paper-and-pencil multiplication P = A × B, where A = 12 and B = 11. We need to add two summands that are shifted versions of A to form the product P = 132. Part b of the figure shows the same example using four-bit binary numbers. Since each digit in B is either 1 or 0, the summands are either shifted versions of A or 0000. Figure 5c shows how each summand can be formed by using the Boolean AND operation of A with the appropriate bit in B. b0 a0 p0 p1 p2 p3 p4 p6 p7 p5 b0 a1 b0 a2 b0 a3 b1 a0 b1 a1 b1 a2 b1 a3 b2 a0 b2 a1 b2 a2 b2 a3 b3 a0 b3 a1 b3 a2 b3 a3 x 1 1 0 0 1 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 b) Binary c) Implementation x a0 a1 a2 a3 b0 b1 b2 b3 x 1 2 1 1 1 2 1 2 1 3 2 a) Decimal Figure 5. Multiplication of binary numbers. A four-bit circuit that implements P = A × B is illustrated in Figure 6. Because of its regular structure, this type of multiplier circuit is usually called an array multiplier. The shaded areas in the circuit correspond to the shaded columns in Figure 5c. In each row of the multiplier AND gates are used to produce the summands, and full adder modules are used to generate the required sums. 5
i6i666 但 的的的这 的的 Figure 6.An array multiplier circuit. Use the following steps to implement the array multiplier circuit 1.Create anew Quartus II project which will be used toimplement the desired circuit on the Altera DE2 board. 2.Generate the required VHDLfile,include it n your project,and compile the circui 3.Use functional simulation to verify that your code is correct 4.Au respectively.The result P=Ax B is to be displayed on HEXI and HEX0. 5.Assign the pins on the FPGA to connect to the switches and 7-segment displays,as indicated in the User Manual for the DE2 board. 6.Recompile the circuit and download it into the FPGA chip. 7.Test the functionality of your design by toggling the switches and observing the 7-segment displays. 6
a1 FA ci b a co s FA ci b a co s a2 a3 b0 b1 b2 a0 FA ci b a co s b3 a0 FA ci b a co s FA ci b a co s a1 a2 0 FA ci b a co s a0 a1 0 0 a0 a2 FA ci b a co s FA ci b a co s a3 a1 FA ci b a co s 0 a3 FA ci b a co s a2 FA ci b a co s a3 FA ci b a co s p0 p1 p2 p3 p4 p6 p7 p5 Figure 6. An array multiplier circuit. Use the following steps to implement the array multiplier circuit: 1. Create a new Quartus II project which will be used to implement the desired circuit on the Altera DE2 board. 2. Generate the required VHDL file, include it in your project, and compile the circuit. 3. Use functional simulation to verify that your code is correct. 4. Augment your design to use switches SW11−8 to represent the number A and switches SW3−0 to represent B. The hexadecimal values of A and B are to be displayed on the 7-segment displays HEX6 and HEX4, respectively. The result P = A × B is to be displayed on HEX1 and HEX0. 5. Assign the pins on the FPGA to connect to the switches and 7-segment displays, as indicated in the User Manual for the DE2 board. 6. Recompile the circuit and download it into the FPGA chip. 7. Test the functionality of your design by toggling the switches and observing the 7-segment displays. 6
Part VI Extend your multiplier to multiply 8-bit numbersand produce a 16-bit product.Use switches SW to represent the numbe 4y the X B n fo the registered adder in Figure 1. After successfully compiling and testing your multiplier circuit,examine the results produced by the Quartus Anayer to the ax ofyour cirut What is th path in of delay beeen Part VII Change your VHDL code to implemen module from th ofthe numroem(LE)nedeand the ciruit Part VIll It many applications of digital circuits it is useful to be able to perform some number of multiplications and then produce a summation of the results.For this part of the exercise you are to design a circuit that performs the calculation S=(A×B)+(C×D) The inputs A.B.C.and D are eight-bit unsig ned numbers.and S provides a 16-bit result.Your circuit should also provide a carry-out signal,All of the inputs and outputs of the circuit should be registered,similar to the structure shown in Figure 1b 1.Create a new Quartus lI project which will be used to implement the desired circuit on the Altera DE2 board Use the Ipmmult and Ipm_add_sub modules to realize the multipliers and adders in your design. nd C to witches SW5- s and cor es SW7-0.Use wEo动oda inpata to be aded in when an act clock edge occurs.while setting WEtoshould prevent loading of these registers. 3.Use KEYo as an active-low asynchronous reset input,and use KEY as a manual clock input 4BziEsncn 6.It is often articular mec th in the form ofmnconsThe procedure for using timing constraints in the Quartus IICAD system is described in the tutorial Timing Considerationswith VHDL-Based Designs,which is available on the DE2 System CD and in the University Program section of Altera's web site. For this exercise we are using a manual clock that is applied by a pushbutton switch,so no realistic timing requirements ex But to demon s involved,assume that your circuit is required to The Tim due tothelengtofariousesterto-register paths in the circuit Examine the tmn analysis report and describe briefly the timing violations observed
Part VI Extend your multiplier to multiply 8-bit numbers and produce a 16-bit product. Use switches SW 15−8 to represent the number A and switches SW7−0 to represent B. The hexadecimal values of A and B are to be displayed on the 7-segment displays HEX7−6 and HEX5−4, respectively. The result P = A × B is to be displayed on HEX3−0. Add registers to your circuit to store the values of A, B, and the product P, using a similar structure as shown for the registered adder in Figure 1. After successfully compiling and testing your multiplier circuit, examine the results produced by the Quartus II Timing Analyzer to determine the fmax of your circuit. What is the longest path in terms of delay between registers? Part VII Change your VHDL code to implement the 8 x 8 multiplier by using the lpm mult module from the library of parameterized modules in the Quartus II system. Complete the design steps above. Compare the results in terms of the number of logic elements (LEs) needed and the circuit fmax. Part VIII It many applications of digital circuits it is useful to be able to perform some number of multiplications and then produce a summation of the results. For this part of the exercise you are to design a circuit that performs the calculation S = (A × B)+(C × D) The inputs A, B, C, and D are eight-bit unsigned numbers, and S provides a 16-bit result. Your circuit should also provide a carry-out signal, Cout. All of the inputs and outputs of the circuit should be registered, similar to the structure shown in Figure 1b. 1. Create a new Quartus II project which will be used to implement the desired circuit on the Altera DE2 board. Use the lpm mult and lpm add sub modules to realize the multipliers and adders in your design. 2. Connect the inputs A and C to switches SW15−8 and connect the inputs B and D to switches SW7−0. Use switch SW16 to select between these two sets of inputs: A, B or C, D. Also, use the switch SW17 as a write enable (WE) input. Setting WE to 1 should allow data to be loaded into the input registers when an active clock edge occurs, while setting WE to 0 should prevent loading of these registers. 3. Use KEY0 as an active-low asynchronous reset input, and use KEY 1 as a manual clock input. 4. Display the hexadecimal value of either A or C, as selected by SW16, on displays HEX7-6 and display either B or D on HEX5-4. The sum S should be shown on HEX3-0, and the C out signal should appear on LEDG8. 5. Compile your code and use either functional or timing simulation to verify that your circuit works properly. Then download the circuit onto the DE2 board and test its operation. 6. It is often necessary to ensure that a digital circuit is able to meet certain speed requirements, such as a particular frequency of a signal applied to a clock input. Such requirements are provided to a CAD system in the form of timing constraints. The procedure for using timing constraints in the Quartus II CAD system is described in the tutorial Timing Considerations with VHDL-Based Designs, which is available on the DE2 System CD and in the University Program section of Altera’s web site. For this exercise we are using a manual clock that is applied by a pushbutton switch, so no realistic timing requirements exist. But to demonstrate the design issues involved, assume that your circuit is required to operate with a clock frequency of 220 MHz. Enter this frequency as a timing constraint in the Quartus II software, and recompile your project. The Timing Analyzer should report that it is unable to meet the timing requirements due to the lengths of various register-to-register paths in the circuit. Examine the timing analysis report and describe briefly the timing violations observed. 7
ters are often called multipliers and the adder.Recompile your project and discuss the results obtained. PartIX sa predes odule add tha modules.Test your circuit using both simulation and by downloading the circuit onto the DE2 board. Briefly describe how the implementation of your circuit differs when using thealadd module.Examine its performance both with and without the pipeline registers discussed in Part VIll Copyright 2006 Altera Corporation. 8
7. One way to increase the speed of operation of a given circuit is to insert registers into the circuit in a way that shortens the lengths of its longest paths. This technique is referred to as pipelining a circuit, and the inserted registers are often called pipeline registers. Insert pipeline registers into your design between the multipliers and the adder. Recompile your project and discuss the results obtained. Part IX The Quartus II software includes a predesigned module called altmult add that can perform calculations of the form S = (A × B)+(C × D). Repeat Part VIII using this module instead of the lpm mult and lpm add sub modules. Test your circuit using both simulation and by downloading the circuit onto the DE2 board. Briefly describe how the implementation of your circuit differs when using the altmult add module. Examine its performance both with and without the pipeline registers discussed in Part VIII. Copyright c 2006 Altera Corporation. 8
