Aside: Clocking Methodologies a The clocking methodology defines when data in a state element is valid and stable relative to the clock State elements-a memory element such as a register Edge-triggered-all state changes occur on a clock edge a Typical execution read contents of state elements - send values through combinational logic -> write results to one or more state elements State Combinational State element logic element 2 clock one clock cycle O Assumes state elements are written on every clock cycle; if not, need explicit write control signal write occurs only when both the write control is asserted and the clock edge occurs 日209 Chapter4A.4 CSE SJTU, 2017EI209 Chapter 4A.4 CSE, SJTU, 2017 Aside: Clocking Methodologies ❑ The clocking methodology defines when data in a state element is valid and stable relative to the clock State elements - a memory element such as a register Edge-triggered – all state changes occur on a clock edge ❑ Typical execution read contents of state elements -> send values through combinational logic -> write results to one or more state elements State element 1 State element 2 Combinational logic clock one clock cycle ❑ Assumes state elements are written on every clock cycle; if not, need explicit write control signal write occurs only when both the write control is asserted and the clock edge occurs