The Processor: Datapath Control a Our implementation of the miPs is simplified memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beg, j a generic implementation use the program counter(PC)to supply Fetch the instruction address and fetch the =PC+4 instruction from memory(and update the PC) Exec Decode decode the instruction (and read registers) execute the instruction a All instructions(except j)use the ALU after reading the registers How? memory-reference? arithmetic? control flow? 日209 Chapter4A.3 CSE SJTU, 2017EI209 Chapter 4A.3 CSE, SJTU, 2017 ❑ Our implementation of the MIPS is simplified memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j ❑ Generic implementation use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) decode the instruction (and read registers) execute the instruction ❑ All instructions (except j) use the ALU after reading the registers How? memory-reference? arithmetic? control flow? The Processor: Datapath & Control Fetch PC = PC+4 Exec Decode