ON MT9M001:1/2-Inch Megapixel Digital Ima ion Serial Bus Description e sensor is a two- re serial ertace slave anc out of the through the serial data (SDATA)line.The SDATA line is pulled up 3.3V off-chip by a 1.5KQ resistor.Either the slave or master device can pull the SDATA line Protocol The two-wire serial interface defines several different transmission codes,as follows: ·astart bit .the slave device eight-bit address a(an)(no)acknowledge bit an 8-bit message ·a stop bit Sequence ethe start ad o rite w indicates a read.The slave device acknowledges its address by sending an acknowledge bit back to the master. vite,t which a Th address has been received.The master then transfers the data eight bits at a time,with the slave sending an acknowledge bit after each eight bits.The MT9M001 uses 16-bit interal registers.thusr equing two 8 t transters to write to on the next 16 bits are written to the next register address.The master stops writing by sending a start or stop bit. A typical read s eaRa as fo First the master sends the write- register data eight bits at a time.The master sends an acknowledge bit after each 8-bit nsfer.The register address is Bus Idle State The bus is idle when both the data and clock lines are HIGH.Control of the bus is initi- ated with a start bit,and the bus is released with a stop bit.Only the master can generate the start and stop bits Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGh.MT9M001_DS Rev. M Pub. 5/15 EN 13 ©Semiconductor Components Industries, LLC,2015. MT9M001: 1/2-Inch Megapixel Digital Image Sensor Serial Bus Description Serial Bus Description Registers are written to and read from the MT9M001 through the two-wire serial inter￾face bus. The sensor is a two-wire serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out of the MT9M001 through the serial data (SDATA) line. The SDATA line is pulled up to 3.3V off-chip by a 1.5K resistor. Either the slave or master device can pull the SDATA line down—the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. Protocol The two-wire serial interface defines several different transmission codes, as follows: • a start bit • the slave device eight-bit address • a(an) (no) acknowledge bit • an 8-bit message • a stop bit Sequence A typical read or write sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's eight-bit address. The last bit of the address determines if the request will be a read or a write, where a “0” indicates a write and a “1” indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the 8-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. The MT9M001 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data eight bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi￾ated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH