Q2 is pulled to a high potential with another resistor and, as a result, turns on Q4 so that it appears as a short in the top part of the totem pole. The saturated Q4 transistor provides a low resistance path from Vcc to the output, producing a high output result for a low input into the inverter. A TTL NAND gate is very similar to the inverter circuit, with the exception that the input coupling transistor Q1 is constructed with multiple emitter-base junctions and each input to the NANd is connected to a separate emitter terminal. Any of the transistor's multiple emitters can be used to turn on Q1. The TTL NAND gate thus functions in the same manner as the inverter in that if any of the nand gate inputs are low, the same circuit action will take place as with a low input to the inverter. Therefore, any time a low input is applied to the nand gate it will produce a high ouput. Only if all of the nand gate inputs are simultaneously high will it then produce the same circuit action as the inverter with its single input high, and the resultant output will low. Input coupling transistors with up to eight emitter-base junctions, and therefore, eight input NAND Storage time(the time it takes for the transistor to come out of saturation) is a major factor of propagation lelay for saturated BJT transistors. A long storage time limits the switching speed of a standard TTL circuit The propagation delay can be decreased and, therefore, the switching speed can be increased, by placing a hottky diode between the base and collector of each transistor that might saturate. The resulting Schottky clamped transistors do not go into saturation(effectively eliminating storage time)since the diode shunts current from the base into the collector before the transistor can achieve saturation. Today, digital circuit designs plemented with TTL logic almost exclusively use one of the Schottky subfamilies to take advantage of the significant improvement in switching speed CMOS Logic Family The active switching element used in all CMOS family circuits is the metal-oxide semiconductor field-effect transistor(MOSFET). CMOS stands for complementary MOS transistors and refers to the use of both type of MOSFET transistors, n-channel and p-channel, in the design of this type of switching circuit. While the physical construction and the internal physics of a MOSFET are quite different from that of the Bjt, the circuit switching action of the two transistor types is quite similar. The MOSFET switch is essentially turned off and has a very high channel resistance by applying the same potential to the gate terminal as the source. An n- channel MOSFEt is turned on and has a very low channel resistance when a high voltage with respect to the ource is applied to the gate. A p-channel MOSFET operates in the same fashion but with opposite polarities; the gate must be more negative than the source to turn on the transistor. a block diagram and schematic for a CMOS inverter circuit is shown in Fig. 79. 2. Note that it is a simpl and much more compact circuit design than that for the TTL inverter. That fact is a major reason why MOSFET integrated circuits have a much higher circuit density than B]T integrated circuits and is one advantage that MOSFET ICs have over BJT ICs. As a result, CMOS is used in all levels of integration, from SSI through VLSI (very large scale integration) When a high logic level is applied to the inverter's input, the p-channel MOSFET QI will be turned off and the n-channel MOSFET Q2 will be turned on. This will cause the output to be shorted to ground through the low resistance path of Q2s channel. The turned off Q1 has a very high channel resistance and acts nearly like an open. When a low logic level is applied to the inverter's input, the p-channel MOSFET Q1 will be turned on and nannel MOSFET Q2 will be turned off. This will cause the output to be shorted to Vpp through the low resistance path of Q1's channel. The turned off Q2 has a very high channel resistance and acts nearly like an open CMOS NAND gates are constructed by paralleling P-channel MOSFETs, one for each input, and putting ries an n-channel MOSFET for each input, as shown in the block diagram and schematic of Fig. 79.3. The nAnd gate will produce a low output only when both Q3 and Q4 are turned on, creating a low resistance path from the output to ground through the two series channels. This can be accomplished by having a high on both input A and input B. This input condition will also turn off Q1 and Q2. If either input A or input B or both is low, the respective parallel MOSFET will be turned on, providing a low resistance path for the output to Vop This will also turn off at least one of the series MOSFETs, resulting in a high resistance path for the output to ground. e 2000 by CRC Press LLC© 2000 by CRC Press LLC Q2 is pulled to a high potential with another resistor and, as a result, turns on Q4 so that it appears as a short in the top part of the totem pole. The saturated Q4 transistor provides a low resistance path from VCC to the output, producing a high output result for a low input into the inverter. A TTL NAND gate is very similar to the inverter circuit, with the exception that the input coupling transistor Q1 is constructed with multiple emitter-base junctions and each input to the NAND is connected to a separate emitter terminal. Any of the transistor’s multiple emitters can be used to turn on Q1. The TTL NAND gate thus functions in the same manner as the inverter in that if any of the NAND gate inputs are low, the same circuit action will take place as with a low input to the inverter. Therefore, any time a low input is applied to the NAND gate it will produce a high ouput. Only if all of the NAND gate inputs are simultaneously high will it then produce the same circuit action as the inverter with its single input high, and the resultant output will be low. Input coupling transistors with up to eight emitter-base junctions, and therefore, eight input NAND gates, are constructed. Storage time (the time it takes for the transistor to come out of saturation) is a major factor of propagation delay for saturated BJT transistors. A long storage time limits the switching speed of a standard TTL circuit. The propagation delay can be decreased and, therefore, the switching speed can be increased, by placing a Schottky diode between the base and collector of each transistor that might saturate. The resulting Schottky￾clamped transistors do not go into saturation (effectively eliminating storage time) since the diode shunts current from the base into the collector before the transistor can achieve saturation. Today, digital circuit designs implemented with TTL logic almost exclusively use one of the Schottky subfamilies to take advantage of the significant improvement in switching speed. CMOS Logic Family The active switching element used in all CMOS family circuits is the metal-oxide semiconductor field-effect transistor (MOSFET). CMOS stands for complementary MOS transistors and refers to the use of both types of MOSFET transistors, n-channel and p-channel, in the design of this type of switching circuit. While the physical construction and the internal physics of a MOSFET are quite different from that of the BJT, the circuit switching action of the two transistor types is quite similar. The MOSFET switch is essentially turned off and has a very high channel resistance by applying the same potential to the gate terminal as the source. An n￾channel MOSFET is turned on and has a very low channel resistance when a high voltage with respect to the source is applied to the gate. A p-channel MOSFET operates in the same fashion but with opposite polarities; the gate must be more negative than the source to turn on the transistor. A block diagram and schematic for a CMOS inverter circuit is shown in Fig. 79.2. Note that it is a simpler and much more compact circuit design than that for the TTL inverter. That fact is a major reason why MOSFET integrated circuits have a much higher circuit density than BJT integrated circuits and is one advantage that MOSFET ICs have over BJT ICs. As a result, CMOS is used in all levels of integration, from SSI through VLSI (very large scale integration). When a high logic level is applied to the inverter’s input, the p-channel MOSFET Q1 will be turned off and the n-channel MOSFET Q2 will be turned on. This will cause the output to be shorted to ground through the low resistance path of Q2’s channel. The turned off Q1 has a very high channel resistance and acts nearly like an open. When a low logic level is applied to the inverter’s input, the p-channel MOSFET Q1 will be turned on and the n-channel MOSFET Q2 will be turned off. This will cause the output to be shorted to VDD through the low resistance path of Q1’s channel. The turned off Q2 has a very high channel resistance and acts nearly like an open. CMOS NAND gates are constructed by paralleling p-channel MOSFETs, one for each input, and putting in series an n-channel MOSFET for each input, as shown in the block diagram and schematic of Fig. 79.3. The NAND gate will produce a low output only when both Q3 and Q4 are turned on, creating a low resistance path from the output to ground through the two series channels. This can be accomplished by having a high on both input A and input B. This input condition will also turn off Q1 and Q2 . If either input A or input B or both is low, the respective parallel MOSFET will be turned on, providing a low resistance path for the output to VDD. This will also turn off at least one of the series MOSFETs, resulting in a high resistance path for the output to ground