Moss, G L, Graham, P, Sandige, R.S., Hinton, H.S. Logic Elements The Electrical Engineering Handbook Ed. Richard C. Dorf Boca raton crc Press llc. 2000
Moss, G.L., Graham, P., Sandige, R.S., Hinton, H.S. “Logic Elements” The Electrical Engineering Handbook Ed. Richard C. Dorf Boca Raton: CRC Press LLC, 2000
79 Logic Elements 79.1 IC Logic Family Operation and Characteristics Logic Family. ECL Logic Family. Logic Family Circuit Mos C Logic Families and Subfamilies. TTL Logic Family Gregory L. Moss Logic families Purdue University 79.2 Logic Gates (IC Peter graham Gate Specification Parameters. Bipolar Transistor Florida Atlantic University(Retired) Gates. Complementary Metal-Oxide Semiconductor(CMOS) Logic Choosing a Logic Family Richard S. Sandige 79.3 Bistable Devices Basic Latches· Gated Latches·Flip- Flops·ldge- Triggered Flip H. S. Hinton Flops. Special Notes on Usi University of colorado 79.4 Optical Devices All-Optical Devices. Optoelectronic Devices. Limitations 79.1 IC Logic Family Operation and Characteristics Gregory L. Moss Digital logic circuits can be classified as belonging to one of two categories, either combinational (also called combinatorial)or sequential logic circuits. The output logic level of a combinatorial circuit depends only on the current logic levels present at the circuit's inputs Sequential logic circuits, on the other hand, have a memory characteristic so the sequential circuit's output is dependent not only on the current input conditions but also on the current output state of the circuit. The primary building block in combinational circuits is the logic gate. The three simplest logic gate functions are the inverter (or NOT), AND, and OR Other common basic logic functions are derived from these three. Table 79.1 gives truth table definitions of the various types of logic gates. The memory elements used to construct sequential logic circuits are called latches and flip-flops The integrated circuit switching logic used in modern digital systems will generally be from one of three families: transistor-transistor logic(TTL), complementary metal-oxide semiconductor logic(CMOS), or emit ter-coupled logic(ECL). Each of the logic families has its advantages and disadvantages. The three major families are also divided into various subfamilies derived from performance improvements in integrated circuit(IC) design technology. Bipolar transistors provide the switching action in both TTl and ECL families, while enhancement-mode MOS transistors are the basis for the CMOS family. Recent improvements in switching circuit performance are also attained using BiCMOS technology, the merging of bipolar and CMOS technologies on a single chip. a particular logic family is usually selected by digital designers based on such criteria as 1. Switching speec 3. PC board area requirements(levels of integration) 4. Output drive capability(fan-out) 5. Noise immunity characteristics 6. Product breadth 7. Sourcing of components c 2000 by CRC Press LLC
© 2000 by CRC Press LLC 79 Logic Elements 79.1 IC Logic Family Operation and Characteristics IC Logic Families and Subfamilies • TTL Logic Family • CMOS Logic Family • ECL Logic Family • Logic Family Circuit Parameters • Interfacing Between Logic Families 79.2 Logic Gates (IC) Gate Specification Parameters • Bipolar Transistor Gates • Complementary Metal-Oxide Semiconductor (CMOS) Logic • Choosing a Logic Family 79.3 Bistable Devices Basic Latches • Gated Latches • Flip-Flops • Edge-Triggered FlipFlops • Special Notes on Using Latches and Flip-Flops 79.4 Optical Devices All-Optical Devices • Optoelectronic Devices • Limitations 79.1 IC Logic Family Operation and Characteristics Gregory L. Moss Digital logic circuits can be classified as belonging to one of two categories, either combinational (also called combinatorial) or sequential logic circuits. The output logic level of a combinatorial circuit depends only on the current logic levels present at the circuit’s inputs. Sequential logic circuits, on the other hand, have a memory characteristic so the sequential circuit’s output is dependent not only on the current input conditions but also on the current output state of the circuit. The primary building block in combinational circuits is the logic gate. The three simplest logic gate functions are the inverter (or NOT), AND, and OR. Other common basic logic functions are derived from these three. Table 79.1 gives truth table definitions of the various types of logic gates. The memory elements used to construct sequential logic circuits are called latches and flip-flops. The integrated circuit switching logic used in modern digital systems will generally be from one of three families: transistor-transistor logic (TTL), complementary metal-oxide semiconductor logic (CMOS), or emitter-coupled logic (ECL). Each of the logic families has its advantages and disadvantages. The three major families are also divided into various subfamilies derived from performance improvements in integrated circuit (IC) design technology. Bipolar transistors provide the switching action in both TTL and ECL families, while enhancement-mode MOS transistors are the basis for the CMOS family. Recent improvements in switching circuit performance are also attained using BiCMOS technology, the merging of bipolar and CMOS technologies on a single chip. A particular logic family is usually selected by digital designers based on such criteria as 1. Switching speed 2. Power dissipation 3. PC board area requirements (levels of integration) 4. Output drive capability (fan-out) 5. Noise immunity characteristics 6. Product breadth 7. Sourcing of components Gregory L. Moss Purdue University Peter Graham Florida Atlantic University (Retired) Richard S. Sandige University of Wyoming H. S. Hinton University of Colorado
TABLE 79.1 Defining Truth Tables for Logic Gates 1-Input Function 2-Input Functions Input Output Inputs Output Functions NOT A B AND OR NAND NOR XOR XNOR 0 0101 1110 1000 0110 TABLE 79.2 Logic Families and Subfamilies Family and Subfamily Description Transistor-transistor logic Standard ttl Low-power TTL High-speed TTL Schottky TTL 74ASXX dvanced Schottky TTL dvanced low-power Schottky TTL Fast TTL andard CMOS Standard CMOS using TTL numbering syster High-speed CMOS High-speed CMOS-TTL compatible Fast CMOS-TTL compatible 74ACxX dvanced CMOS 74ACTXX Advanced CMOS--TTL compatible CMOS-TTL compatib ECL (or CML Emitter-coupled (current-mode)logic Standard eCL 10Hxx High-speed ECL IC Logic Families and Subfamilies The integrated circuit logic families actually consist of several subfamilies of ICs that differ in various perfor- nance characteristics. The TTl logic family has been the most widely used family type for applications that employ small-scale integration(SSI)or medium-scale integration(MSI) integrated circuits. Lower power consumption and higher levels of integration are the principal advantages of the CMOS family. The ECL family is generally used in applications that require high-speed switching logic. Today, the most common device lumbering system used in the TTL and CMOS families has a prefix of 54 (generally used in military applications and having an operating temperature range of-55 to 125.C)and 74(generally used in industrial/commercial plications and having an operating temperature range of 0 to 70oC). Table 79.2 identifies various logic families and su TTL Logic Family The Ttl family has been the most widely used logic family for many years in applications that use SSI and MSI. It is relatively fast and offers a great variety of standard chips The active switching element used in all TTL family circuits is the npn bipolar junction transistor(BjT) e 2000 by CRC Press LLC
© 2000 by CRC Press LLC IC Logic Families and Subfamilies The integrated circuit logic families actually consist of several subfamilies of ICs that differ in various performance characteristics. The TTL logic family has been the most widely used family type for applications that employ small-scale integration (SSI) or medium-scale integration (MSI) integrated circuits. Lower power consumption and higher levels of integration are the principal advantages of the CMOS family. The ECL family is generally used in applications that require high-speed switching logic. Today, the most common device numbering system used in the TTL and CMOS families has a prefix of 54 (generally used in military applications and having an operating temperature range of –55 to 125°C) and 74 (generally used in industrial/commercial applications and having an operating temperature range of 0 to 70°C). Table 79.2 identifies various logic families and subfamilies. TTL Logic Family The TTL family has been the most widely used logic family for many years in applications that use SSI and MSI. It is relatively fast and offers a great variety of standard chips. The active switching element used in all TTL family circuits is the npn bipolar junction transistor (BJT). The transistor is turned on when the base is approximately 0.7 V more positive than the emitter and there is a sufficient amount of base current flowing. The turned on transistor (in non-Schottky subfamilies) is said to TABLE 79.1 Defining Truth Tables for Logic Gates 1-Input Function 2-Input Functions Input Output Inputs Output Functions A NOT A B AND OR NAND NOR XOR XNOR 0 1 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 TABLE 79.2 Logic Families and Subfamilies Family and Subfamily Description TTL Transistor-transistor logic 74xx Standard TTL 74Lxx Low-power TTL 74Hxx High-speed TTL 74Sxx Schottky TTL 74LSxx Low-power Schottky TTL 74ASxx Advanced Schottky TTL 74ALSxx Advanced low-power Schottky TTL 74Fxx Fast TTL CMOS Complementary metal-oxide semiconductor 4xxx Standard CMOS 74Cxx Standard CMOS using TTL numbering system 74HCxx High-speed CMOS 74HCTxx High-speed CMOS—TTL compatible 74FCTxx Fast CMOS—TTL compatible 74ACxx Advanced CMOS 74ACTxx Advanced CMOS—TTL compatible 74AHCxx Advanced high-speed CMOS 74AHCTxx Advanced high-speed CMOS-TTL compatible ECL (or CML) Emitter-coupled (current-mode) logic 10xxx Standard ECL 10Hxxx High-speed ECL
FIGURE 79.1 TTL inverter circuit block diagram and operation. be in saturation and i acts like a closed switch between the collector and emitter terminals. The transistor is turned off when the base is not biased with a high enough voltage(with respect to the emitter). Under this condition, the transistor acts like an open switch between the collector and emitter terminals Figure 79. 1 illustrates the transistor circuit blocks used in a standard TTL inverter. Four transistors are used to achieve the inverter function. The input to the gate connects to the emitter of transistor Q1, the input coupling transistor. a clamping diode on the input prevents negative input voltage spikes from damaging Q1 The collector voltage(and current)of Q1 controls Q2, the phase splitter transistor Q2, in turn, controls the Q3 and Q4 transistors forming the output circuit, which is called a totem-pole arrangement. Q4 serves as a pull-up transistor to pull the output high when it is turned on. Q3 does just the opposite to the output and serves as a pull-down transistor Q3 pulls the output low when it is turned on Only one of the two transistors in the totem pole may be turned on at a time, which is the function of the phase splitter transistor Q2 When a high logic level is applied to the inverters input, Q1's base-emitter junction will be reverse biased and the base-collector junction will be forward biased. This circuit condition will allow Q1 collector current to flow into the base of Q2, saturating Q2 and thereby providing base current into Q3, turning it on also. The collector voltage of Q2 is too low to turn on Q4 so that it appears as an open in the top part of the totem pole the output near ground potential, producing a low output result for a high input into the inverte emitter diode between the two totem-pole transistors provides an extra voltage drop in series with the base-emitter ction of Q4 to ensure that Q4 will be turned off when Q2 is turned on. The saturated Q3 transistor bring When a low logic level is applied to the inverter's input, QIs base-emitter junction will be forward biased and the base-collector junction will be reverse biased. This circuit condition will turn on Q1 so that the collector terminal is shorted to the emitter and, therefore, to ground (low level). This low voltage is also on the base of Q2 and turns Q2 off with Q2 off, there will be insufficient base current into Q3, turning it off also Q2 leakage current is shunted to ground with a resistor to prevent the partial turning on of Q3. The collector voltage of c2000 by CRC Press LLC
© 2000 by CRC Press LLC be in saturation and, ideally, acts like a closed switch between the collector and emitter terminals. The transistor is turned off when the base is not biased with a high enough voltage (with respect to the emitter). Under this condition, the transistor acts like an open switch between the collector and emitter terminals. Figure 79.1 illustrates the transistor circuit blocks used in a standard TTL inverter. Four transistors are used to achieve the inverter function. The input to the gate connects to the emitter of transistor Q1, the input coupling transistor. A clamping diode on the input prevents negative input voltage spikes from damaging Q1. The collector voltage (and current) of Q1 controls Q2, the phase splitter transistor. Q2, in turn, controls the Q3 and Q4 transistors forming the output circuit, which is called a totem-pole arrangement. Q4 serves as a pull-up transistor to pull the output high when it is turned on. Q3 does just the opposite to the output and serves as a pull-down transistor. Q3 pulls the output low when it is turned on. Only one of the two transistors in the totem pole may be turned on at a time, which is the function of the phase splitter transistor Q2. When a high logic level is applied to the inverter’s input, Q1’s base-emitter junction will be reverse biased and the base-collector junction will be forward biased. This circuit condition will allow Q1 collector current to flow into the base of Q2, saturating Q2 and thereby providing base current into Q3, turning it on also. The collector voltage of Q2 is too low to turn on Q4 so that it appears as an open in the top part of the totem pole. A diode between the two totem-pole transistors provides an extra voltage drop in series with the base-emitter junction of Q4 to ensure that Q4 will be turned off when Q2 is turned on. The saturated Q3 transistor brings the output near ground potential, producing a low output result for a high input into the inverter. When a low logic level is applied to the inverter’s input, Q1’s base-emitter junction will be forward biased and the base-collector junction will be reverse biased. This circuit condition will turn on Q1 so that the collector terminal is shorted to the emitter and, therefore, to ground (low level). This low voltage is also on the base of Q2 and turns Q2 off. With Q2 off, there will be insufficient base current into Q3, turning it off also. Q2 leakage current is shunted to ground with a resistor to prevent the partial turning on of Q3. The collector voltage of FIGURE 79.1 TTL inverter circuit block diagram and operation
Q2 is pulled to a high potential with another resistor and, as a result, turns on Q4 so that it appears as a short in the top part of the totem pole. The saturated Q4 transistor provides a low resistance path from Vcc to the output, producing a high output result for a low input into the inverter. A TTL NAND gate is very similar to the inverter circuit, with the exception that the input coupling transistor Q1 is constructed with multiple emitter-base junctions and each input to the NANd is connected to a separate emitter terminal. Any of the transistor's multiple emitters can be used to turn on Q1. The TTL NAND gate thus functions in the same manner as the inverter in that if any of the nand gate inputs are low, the same circuit action will take place as with a low input to the inverter. Therefore, any time a low input is applied to the nand gate it will produce a high ouput. Only if all of the nand gate inputs are simultaneously high will it then produce the same circuit action as the inverter with its single input high, and the resultant output will low. Input coupling transistors with up to eight emitter-base junctions, and therefore, eight input NAND Storage time(the time it takes for the transistor to come out of saturation) is a major factor of propagation lelay for saturated BJT transistors. A long storage time limits the switching speed of a standard TTL circuit The propagation delay can be decreased and, therefore, the switching speed can be increased, by placing a hottky diode between the base and collector of each transistor that might saturate. The resulting Schottky clamped transistors do not go into saturation(effectively eliminating storage time)since the diode shunts current from the base into the collector before the transistor can achieve saturation. Today, digital circuit designs plemented with TTL logic almost exclusively use one of the Schottky subfamilies to take advantage of the significant improvement in switching speed CMOS Logic Family The active switching element used in all CMOS family circuits is the metal-oxide semiconductor field-effect transistor(MOSFET). CMOS stands for complementary MOS transistors and refers to the use of both type of MOSFET transistors, n-channel and p-channel, in the design of this type of switching circuit. While the physical construction and the internal physics of a MOSFET are quite different from that of the Bjt, the circuit switching action of the two transistor types is quite similar. The MOSFET switch is essentially turned off and has a very high channel resistance by applying the same potential to the gate terminal as the source. An n- channel MOSFEt is turned on and has a very low channel resistance when a high voltage with respect to the ource is applied to the gate. A p-channel MOSFET operates in the same fashion but with opposite polarities; the gate must be more negative than the source to turn on the transistor. a block diagram and schematic for a CMOS inverter circuit is shown in Fig. 79. 2. Note that it is a simpl and much more compact circuit design than that for the TTL inverter. That fact is a major reason why MOSFET integrated circuits have a much higher circuit density than B]T integrated circuits and is one advantage that MOSFET ICs have over BJT ICs. As a result, CMOS is used in all levels of integration, from SSI through VLSI (very large scale integration) When a high logic level is applied to the inverter's input, the p-channel MOSFET QI will be turned off and the n-channel MOSFET Q2 will be turned on. This will cause the output to be shorted to ground through the low resistance path of Q2s channel. The turned off Q1 has a very high channel resistance and acts nearly like an open. When a low logic level is applied to the inverter's input, the p-channel MOSFET Q1 will be turned on and nannel MOSFET Q2 will be turned off. This will cause the output to be shorted to Vpp through the low resistance path of Q1's channel. The turned off Q2 has a very high channel resistance and acts nearly like an open CMOS NAND gates are constructed by paralleling P-channel MOSFETs, one for each input, and putting ries an n-channel MOSFET for each input, as shown in the block diagram and schematic of Fig. 79.3. The nAnd gate will produce a low output only when both Q3 and Q4 are turned on, creating a low resistance path from the output to ground through the two series channels. This can be accomplished by having a high on both input A and input B. This input condition will also turn off Q1 and Q2. If either input A or input B or both is low, the respective parallel MOSFET will be turned on, providing a low resistance path for the output to Vop This will also turn off at least one of the series MOSFETs, resulting in a high resistance path for the output to ground. e 2000 by CRC Press LLC
© 2000 by CRC Press LLC Q2 is pulled to a high potential with another resistor and, as a result, turns on Q4 so that it appears as a short in the top part of the totem pole. The saturated Q4 transistor provides a low resistance path from VCC to the output, producing a high output result for a low input into the inverter. A TTL NAND gate is very similar to the inverter circuit, with the exception that the input coupling transistor Q1 is constructed with multiple emitter-base junctions and each input to the NAND is connected to a separate emitter terminal. Any of the transistor’s multiple emitters can be used to turn on Q1. The TTL NAND gate thus functions in the same manner as the inverter in that if any of the NAND gate inputs are low, the same circuit action will take place as with a low input to the inverter. Therefore, any time a low input is applied to the NAND gate it will produce a high ouput. Only if all of the NAND gate inputs are simultaneously high will it then produce the same circuit action as the inverter with its single input high, and the resultant output will be low. Input coupling transistors with up to eight emitter-base junctions, and therefore, eight input NAND gates, are constructed. Storage time (the time it takes for the transistor to come out of saturation) is a major factor of propagation delay for saturated BJT transistors. A long storage time limits the switching speed of a standard TTL circuit. The propagation delay can be decreased and, therefore, the switching speed can be increased, by placing a Schottky diode between the base and collector of each transistor that might saturate. The resulting Schottkyclamped transistors do not go into saturation (effectively eliminating storage time) since the diode shunts current from the base into the collector before the transistor can achieve saturation. Today, digital circuit designs implemented with TTL logic almost exclusively use one of the Schottky subfamilies to take advantage of the significant improvement in switching speed. CMOS Logic Family The active switching element used in all CMOS family circuits is the metal-oxide semiconductor field-effect transistor (MOSFET). CMOS stands for complementary MOS transistors and refers to the use of both types of MOSFET transistors, n-channel and p-channel, in the design of this type of switching circuit. While the physical construction and the internal physics of a MOSFET are quite different from that of the BJT, the circuit switching action of the two transistor types is quite similar. The MOSFET switch is essentially turned off and has a very high channel resistance by applying the same potential to the gate terminal as the source. An nchannel MOSFET is turned on and has a very low channel resistance when a high voltage with respect to the source is applied to the gate. A p-channel MOSFET operates in the same fashion but with opposite polarities; the gate must be more negative than the source to turn on the transistor. A block diagram and schematic for a CMOS inverter circuit is shown in Fig. 79.2. Note that it is a simpler and much more compact circuit design than that for the TTL inverter. That fact is a major reason why MOSFET integrated circuits have a much higher circuit density than BJT integrated circuits and is one advantage that MOSFET ICs have over BJT ICs. As a result, CMOS is used in all levels of integration, from SSI through VLSI (very large scale integration). When a high logic level is applied to the inverter’s input, the p-channel MOSFET Q1 will be turned off and the n-channel MOSFET Q2 will be turned on. This will cause the output to be shorted to ground through the low resistance path of Q2’s channel. The turned off Q1 has a very high channel resistance and acts nearly like an open. When a low logic level is applied to the inverter’s input, the p-channel MOSFET Q1 will be turned on and the n-channel MOSFET Q2 will be turned off. This will cause the output to be shorted to VDD through the low resistance path of Q1’s channel. The turned off Q2 has a very high channel resistance and acts nearly like an open. CMOS NAND gates are constructed by paralleling p-channel MOSFETs, one for each input, and putting in series an n-channel MOSFET for each input, as shown in the block diagram and schematic of Fig. 79.3. The NAND gate will produce a low output only when both Q3 and Q4 are turned on, creating a low resistance path from the output to ground through the two series channels. This can be accomplished by having a high on both input A and input B. This input condition will also turn off Q1 and Q2 . If either input A or input B or both is low, the respective parallel MOSFET will be turned on, providing a low resistance path for the output to VDD. This will also turn off at least one of the series MOSFETs, resulting in a high resistance path for the output to ground
Q2 FIGURE 79.2 CMOS inverter circuit block diagram and operation. Q2 transistors FIGURE 79.3 CMOS two-input NAND circuit block diagram and operation. ECL Logic Family ECL is a higher-speed logic family. While it does not offer as large a variety of IC chips as are available in the TTL family, it is quite popular for logic applications requiring high-speed switching The active switching element used in the ECL family circuits is also the npn BJT. Unlike the TTl family, however, which switches the transistors into saturation when turning them on, ECL switching is designed to revent driving the transistors into saturation. Whenever bipolar transistors are driven into saturation, their witching speed will be limited by the charge carrier storage delay, a transistor operational characteristic. Thus, the switching speed of ECL circuits will be significantly higher than for TTL circuits. ECL operation is based c2000 by CRC Press LLC
© 2000 by CRC Press LLC ECL Logic Family ECL is a higher-speed logic family. While it does not offer as large a variety of IC chips as are available in the TTL family, it is quite popular for logic applications requiring high-speed switching. The active switching element used in the ECL family circuits is also the npn BJT. Unlike the TTL family, however, which switches the transistors into saturation when turning them on, ECL switching is designed to prevent driving the transistors into saturation. Whenever bipolar transistors are driven into saturation, their switching speed will be limited by the charge carrier storage delay, a transistor operational characteristic. Thus, the switching speed of ECL circuits will be significantly higher than for TTL circuits. ECL operation is based FIGURE 79.2 CMOS inverter circuit block diagram and operation. FIGURE 79.3 CMOS two-input NAND circuit block diagram and operation
ogio g OH(min) VIH(min Disallow- Indeter- Logic C O FIGURE 79.4 Switching device logic levels TABLE 79. 3 ignal Voltage Parameters for Selected Logic Subfamilies(in 2.0 0.5 74ASxX 0.4 2.0 74FXX 74HCxx 0.1 74HCTxX 0.1 2.0 8888983 74ACxx 0.4 74ACTxx 0.4 74AHCxx 0.1 3.85 74AHCTX 3.65 0.96 1.65 1.105 1.475 10Hxx 148 on switching a fixed amount of bias current that is less than the saturation amount between two different transistors. The basic circuit found in the ECl family is the differential amplifier. One side of the differential amplifier is controlled by a bias circuit and the other is controlled by the logic inputs to the gate. This logic family is also referred to as current-mode logic( CML) because of its current switching operation Logic Family Circuit Parameters Digital circuits and systems operate with only two states, logic I and 0, usually represented by two different voltage levels, a high and a low. The two logic levels actually consist of a range of values with the numerical quantities dependent upon the specific family that is used. Minimum high logic levels and maximum low logic levels are established by specifications for each family. Minimum device output levels for a logic high are called VOH(min) and minimum input levels are called VIH(min). The abbreviations for maximum output and input low logic levels are VoLmax) and VIL(max), respectively. Figure 79.4 shows the relationships between these parameters Logic voltage level parameters are illustrated for selected prominent logic subfamilies in Table 79.3. As seen in this illustration, there are many operational incompatibilities between major logic family types. Noise margin is a quantitative measure of a device's noise immunity. High-level noise margin( VNH)and low-level noise margin( VNL)are defined in Eqs. (79.1)and(79.2). e 2000 by CRC Press LLC
© 2000 by CRC Press LLC on switching a fixed amount of bias current that is less than the saturation amount between two different transistors. The basic circuit found in the ECL family is the differential amplifier. One side of the differential amplifier is controlled by a bias circuit and the other is controlled by the logic inputs to the gate. This logic family is also referred to as current-mode logic (CML) because of its current switching operation. Logic Family Circuit Parameters Digital circuits and systems operate with only two states, logic 1 and 0, usually represented by two different voltage levels, a high and a low. The two logic levels actually consist of a range of values with the numerical quantities dependent upon the specific family that is used. Minimum high logic levels and maximum low logic levels are established by specifications for each family. Minimum device output levels for a logic high are called VOH(min) and minimum input levels are called VIH(min). The abbreviations for maximum output and input low logic levels are VOL(max) and VIL(max), respectively. Figure 79.4 shows the relationships between these parameters. Logic voltage level parameters are illustrated for selected prominent logic subfamilies in Table 79.3. As seen in this illustration, there are many operational incompatibilities between major logic family types. Noise margin is a quantitative measure of a device’s noise immunity. High-level noise margin (VNH) and low-level noise margin (VNL) are defined in Eqs. (79.1) and (79.2). FIGURE 79.4 Switching device logic levels. TABLE 79.3 Logic Signal Voltage Parameters for Selected Logic Subfamilies (in Volts) Subfamily VOH(min) VOL(max) VIH(min) VIL(max) 74xx 2.4 0.4 2.0 0.8 74LSxx 2.7 0.5 2.0 0.8 74ASxx 2.5 0.5 2.0 0.8 74ALSxx 2.5 0.4 2.0 0.8 74Fxx 2.5 0.5 2.0 0.8 74HCxx 4.9 0.1 3.15 0.9 74HCTxx 4.9 0.1 2.0 0.8 74ACxx 3.8 0.4 3.15 1.35 74ACTxx 3.8 0.4 2.0 0.8 74AHCxx 4.5 0.1 3.85 1.65 74AHCTxx 3.65 0.1 2.0 0.8 10xxx –0.96 –1.65 –1.105 –1.475 10Hxxx –0.98 –1.63 –1.13 –1.48
DRIVEN GATE萨 IIH DRIVI DRIVEN GATE HIGH GATE萨2 curre 工H GATE F1 L DRIVEN GATE GATE F2 current ng DRIVEN GATE F FIGURE 79.5 Current loading of driving gates. TABLE 79.4 Worst Case Current Parameters for Selected Logic Subfamilies ubfamil 16 mA AA叭 8 mA 201 8 mA 20uA-100μ 201 0.6mA 74HCxx 4 mA 4AHCXX 74AHCTxX -50 mA -265μA500 10Hxxx 50 mA OH(min)vIH(min) (79.1) (79.2) Using the logic voltage values given in Table 79.3 for the selected subfamilies reveals that highest noise immunity is obtained with logic devices in the CMOS family, while lowest noise immunity is endemic to the ECL family. Switching circuit outputs are loaded by the inputs of the devices that they are driving, as illustrated in Fig. 79.5. Worst case input loading current levels and output driving current capabilities are listed in Table 79.4 for various logic subfamilies. The fan-out of a driving device is the ratio between its output current capabilities at each logic level and the corresponding gate input current loading value. Switching circuits based on bipolar transistors have fan-out limited primarily by the current-sinking and current-sourcing capabilities of the driving c2000 by CRC Press LLC
© 2000 by CRC Press LLC VNH = VOH(min) – VIH(min) (79.1) VNL = VIL(max) – VOL(max) (79.2) Using the logic voltage values given in Table 79.3 for the selected subfamilies reveals that highest noise immunity is obtained with logic devices in the CMOS family, while lowest noise immunity is endemic to the ECL family. Switching circuit outputs are loaded by the inputs of the devices that they are driving, as illustrated in Fig. 79.5. Worst case input loading current levels and output driving current capabilities are listed in Table 79.4 for various logic subfamilies. The fan-out of a driving device is the ratio between its output current capabilities at each logic level and the corresponding gate input current loading value. Switching circuits based on bipolar transistors have fan-out limited primarily by the current-sinking and current-sourcing capabilities of the driving device. FIGURE 79.5 Current loading of driving gates. TABLE 79.4 Worst Case Current Parameters for Selected Logic Subfamilies Subfamily IOH(max) IOL(max) IIH(max) IIL(max) 74xx –400 mA 16 mA 40 mA –1.6 mA 74LSxx –400 mA 8 mA 20 mA –400 mA 74ASxx –2 mA 20 mA 200 mA –2 mA 74ALSxx –400 mA 8 mA 20 mA –100 mA 74Fxx –1 mA 20 mA 20 mA –0.6 mA 74HCxx –4 mA 4 mA 1 mA –1 mA 74HCTxx –4 mA 4 mA 1 mA –1 mA 74ACxx –24 mA 24 mA 1 mA –1 mA 74ACTxx –24 mA 24 mA 1 mA –1 mA 74AHCxx –8 mA 8 mA 1 mA –1 mA 74AHCTxx –8 mA 8 mA 1 mA –1 mA 10xxx 50 mA –50 mA –265 mA 500 nA 10Hxxx 50 mA –50 mA –265 mA 500 nA
TABLE 79.5 Speed-Power Comparison for Selected Logic Subfamilies Static Power Delay Time, Dissipation, Speed-Power p 74x 10 777 74HCTXX 42×10-3 74ACx 0.010 0×10-3 74ACTxx 0.010 0×10-3 74AHCxX 25 10HxXx CMOS switching circuits are limited by the charging and discharging times associated with the output resistance of the driving gate and the input capacitance of the load gates. Thus, CMOS fan-out depends on the frequency of switching. With fewer(capacitive)loading inputs to drive, the maximum switching frequency of cMos devices will increase The switching speed of logic devices is dependent on the device's propagation delay time. The propagation delay of a logic device limits the frequency at which it can be operated. There are two propagation delay times specified for logic gates: tpHL, delay time for the output to change from high to low, and tPLH, delay time for the output to change from low to high. Average typical propagation delay times for a single gate are listed for several logic subfamilies in Table 79.5. The ECL family has the fastest switching speed. The amount of power required by an IC is normally specified in terms of the amount of current Icc (TTL family), IpD(CMOS family), or IEE(ECL family) drawn from the power supply For complex IC devices, the quired supply current is given under specified test conditions For Ttl chips containing simple gates, the average power dissipation Pp(ave) is normally calculated from two measurements, IccH(when all gate outputs high)and Icc (when all gate outputs are low). Table 79.5 compares the static power dissipation of several logic subfamilies. The ECL family has the highest power dissipation, while the lowest is attained with the CMOS family. It should be noted that power dissipation for the CMOS family is directly proportional to the gate input ignal frequency. For example, one would typically find that the power dissipation for a CMOS logic circuit would increase by a factor of 100 if the input signal frequency is increased from 1 kHz to 100 kHz The speed-power product is a relative figure of merit that is calculated by the formula given in Eq. (79. 3) This performance measurement is normally expressed in picojoules(pD) Speed-power product =(tPHL tPLH )/2 X Pp(ave) (79.3) A low value of speed-power product is desirable to implement high-speed(and, therefore, low propagation lelay time) switching devices that consume low amounts of power. Because of the nature of transistor switching circuits, it is difficult to attain high-speed switching with low power dissipation. The continued development f new IC logic families and subfamilies is largely due to the trade-offs between these two device switching parameters. The speed-power product for various subfamilies is also compared in Table 79.5. Interfacing Between Logic Families The interconnection of logic chips requires that input and output specifications be satisfied. Figure 79.6 illus- trates voltage and current requirements. The driving chips VOH(min) must be greater than the driven circuit VIH(minl, and the driver's VOLimax) must be less than VIL(max) for the loading circuit. Voltage level shifters must be e 2000 by CRC Press LLC
© 2000 by CRC Press LLC CMOS switching circuits are limited by the charging and discharging times associated with the output resistance of the driving gate and the input capacitance of the load gates. Thus, CMOS fan-out depends on the frequency of switching. With fewer (capacitive) loading inputs to drive, the maximum switching frequency of CMOS devices will increase. The switching speed of logic devices is dependent on the device’s propagation delay time. The propagation delay of a logic device limits the frequency at which it can be operated. There are two propagation delay times specified for logic gates: tPHL, delay time for the output to change from high to low, and tPLH, delay time for the output to change from low to high. Average typical propagation delay times for a single gate are listed for several logic subfamilies in Table 79.5. The ECL family has the fastest switching speed. The amount of power required by an IC is normally specified in terms of the amount of current ICC (TTL family), IDD (CMOS family), or IEE (ECL family) drawn from the power supply. For complex IC devices, the required supply current is given under specified test conditions. For TTL chips containing simple gates, the average power dissipation PD(ave) is normally calculated from two measurements, ICCH (when all gate outputs are high) and ICCL (when all gate outputs are low). Table 79.5 compares the static power dissipation of several logic subfamilies. The ECL family has the highest power dissipation, while the lowest is attained with the CMOS family. It should be noted that power dissipation for the CMOS family is directly proportional to the gate input signal frequency. For example, one would typically find that the power dissipation for a CMOS logic circuit would increase by a factor of 100 if the input signal frequency is increased from 1 kHz to 100 kHz. The speed-power product is a relative figure of merit that is calculated by the formula given in Eq. (79.3). This performance measurement is normally expressed in picojoules (pJ). Speed-power product = (tPHL + tPLH)/2 ¥ PD(ave) (79.3) A low value of speed-power product is desirable to implement high-speed (and, therefore, low propagation delay time) switching devices that consume low amounts of power. Because of the nature of transistor switching circuits, it is difficult to attain high-speed switching with low power dissipation. The continued development of new IC logic families and subfamilies is largely due to the trade-offs between these two device switching parameters. The speed-power product for various subfamilies is also compared in Table 79.5. Interfacing Between Logic Families The interconnection of logic chips requires that input and output specifications be satisfied. Figure 79.6 illustrates voltage and current requirements. The driving chip’s VOH(min) must be greater than the driven circuit’s VIH(min), and the driver’s VOL(max) must be less than VIL(max) for the loading circuit. Voltage level shifters must be TABLE 79.5 Speed-Power Comparison for Selected Logic Subfamilies Propagation Static Power Delay Time, Dissipation, Speed-Power Subfamily ns (ave.) mW (per gate) Product, pJ 74xx 10 10 100 74LSxx 9.5 2 19 74ASxx 1.5 2 13 74ALSxx 4 1.2 5 74Fxx 3 6 18 74HCxx 8 0.003 24 ¥ 10–3 74HCTxx 14 0.003 42 ¥ 10–3 74ACxx 5 0.010 50 ¥ 10–3 74ACTxx 5 0.010 50 ¥ 10–3 74AHCxx 5.5 0.003 16 ¥ 10–3 74AHCTxx 5 0.003 14 ¥ 10–3 10xxx 2 25 50 10Hxxx 1 25 25
DRIVING ro>工 DRIVEN CIRCUIT FIGURE 79.6 Circuit interfacing requirements. used to interface the circuits together if these voltage requirements are not met. Of course, a driving circuit's output must not exceed the maximum and minimum allowable input voltages for the driven circuit. Also, the current sinking and sourcing ability of the driver circuit's output must be greater than the total current requirements for the loading circuit Buffer gates or stages must be used if current requirements are not satisfied. All chips within a single logic family are designed to be compatible with other chips in the same family. Mixing chips from multiple subfamilies together within a single digital circuit can have adverse effects on the overall circuit's switching speed and noise immunity. Defining Terms Fan-out: The specification used to identify the limit to the number of loading inputs that can be reliably driven by a driving device's output Logic level: The high or low value of a voltage variable that is assigned to be a l or a 0 state. Noise immunity: A logic device s ability to tolerate input voltage fluctuation caused by noise without changing Its output state. Propagation delay time: The time delay from when the input logic level to a device is changed until the resultant output change is produced by that device. Speed-power product: An overall performance measurement that is used to compare the various logic families and subfamilies Truth table: A listing of the relationship of a circuits output that is produced for various combinations of logic levels at the inputs Related Topic 25.3 Application-Specific Integrated Circuits References A P Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic, 1995 D.J. Comer, Digital Logic and State Machine Design, 2nd ed, Philadelphia: Saunders College Publishing, 1990 S. H. K. Embabi, A. Bellaouar, and M. I. Elmasry, Digital BiCMOS Integrated Circuit Design, Boston: Kluwer Academic, 1993 T. L. Floyd, Digital Fundamentals, 5th ed, Columbus, Ohio: Merrill Publishing Company, 1994 K. Gopalan, Introduction to Digital Microelectronic Circuits, Chicago: Irwin, 1996. J. D. Greenfield, Practical Digital Design Using ICs, 3rd ed, Englewood Cliffs, N.J.: Prentice-Hall, 1994 R J Prestopnik, Digital Electronics: Concepts and Applications for Digital Design, Philadelphia: Saunders College Publishing, 1990. R.S. Sandige, Modern Digital Design, New York: McGraw-Hill, 1990. M. Shoji, Theory of CMOS Digital Circuits and Circuit Failures, Princeton, N J: Princeton University Press, 1992. R J. Tocci, Digital Systems: Principles and Applications, 6th ed, Englewood Cliffs, N.J. Prentice-Hall, 1995 S. H Unger, The Essence of Logic Circuits, 2nd ed, New York: IEEE Press, 1996 J. F. Wakerly, Digital Design: Principles and Practices, 2nd ed, Englewood Cliffs, N J: Prentice-Hall, 1994 c2000 by CRC Press LLC
© 2000 by CRC Press LLC used to interface the circuits together if these voltage requirements are not met. Of course, a driving circuit’s output must not exceed the maximum and minimum allowable input voltages for the driven circuit. Also, the current sinking and sourcing ability of the driver circuit’s output must be greater than the total current requirements for the loading circuit. Buffer gates or stages must be used if current requirements are not satisfied. All chips within a single logic family are designed to be compatible with other chips in the same family. Mixing chips from multiple subfamilies together within a single digital circuit can have adverse effects on the overall circuit’s switching speed and noise immunity. Defining Terms Fan-out: The specification used to identify the limit to the number of loading inputs that can be reliably driven by a driving device’s output. Logic level: The high or low value of a voltage variable that is assigned to be a 1 or a 0 state. Noise immunity: A logic device’s ability to tolerate input voltage fluctuation caused by noise without changing its output state. Propagation delay time: The time delay from when the input logic level to a device is changed until the resultant output change is produced by that device. Speed-power product: An overall performance measurement that is used to compare the various logic families and subfamilies. Truth table: A listing of the relationship of a circuit’s output that is produced for various combinations of logic levels at the inputs. Related Topic 25.3 Application-Specific Integrated Circuits References A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic, 1995. D. J. Comer, Digital Logic and State Machine Design, 2nd ed., Philadelphia: Saunders College Publishing, 1990. S. H. K. Embabi, A. Bellaouar, and M. I. Elmasry, Digital BiCMOS Integrated Circuit Design, Boston: Kluwer Academic, 1993. T. L. Floyd, Digital Fundamentals, 5th ed., Columbus, Ohio: Merrill Publishing Company, 1994. K. Gopalan, Introduction to Digital Microelectronic Circuits, Chicago: Irwin, 1996. J. D. Greenfield, Practical Digital Design Using ICs, 3rd ed., Englewood Cliffs, N.J.: Prentice-Hall, 1994. R. J. Prestopnik, Digital Electronics: Concepts and Applications for Digital Design, Philadelphia: Saunders College Publishing, 1990. R. S. Sandige, Modern Digital Design, New York: McGraw-Hill, 1990. M. Shoji, Theory of CMOS Digital Circuits and Circuit Failures, Princeton, N.J.: Princeton University Press, 1992. R. J. Tocci, Digital Systems: Principles and Applications, 6th ed., Englewood Cliffs, N.J.: Prentice-Hall, 1995. S. H. Unger, The Essence of Logic Circuits, 2nd ed., New York: IEEE Press, 1996. J. F. Wakerly, Digital Design: Principles and Practices, 2nd ed., Englewood Cliffs, N.J.: Prentice-Hall, 1994. FIGURE 79.6 Circuit interfacing requirements
