《电子工程师手册》学习资料（英文版）Memory devices 80.pdf_大学文库

80 Memory devices 0.1 Integrated Circuits(RAM, ROM Dynamic RAMs(DRAMs). Static RAMs(SRAMs). Nonvolatile Programmable Memories.Read-Only Memories(ROMs W. David pricer 0.2 Basic Disk system architectures Basic Magnetic Disk System Architecture. Characterization of 1yo Randy h. Katz Workloads. Extensions to Conventional Disk Architectures University of california, Berkeley 80.3 Magnet A Brief Historical Review. Introduction. Magnetic Tape. Tape Peter A. Lee Format. Recording Modes Department of Trade and Industry 80.4 Magneto-Optical Disk Data Storage Preliminaries and Basic Definitions. The Optical Path. Automatic Focusing. Automatic Tracking Thermomagnetic Recording M. Mansuripur Process. Magneto-Optical Readout. Materials of Magneto-Optical University of Arizona, Tucson Data Storage 80.1 Integrated Circuits(RAM, ROM) W. David pricer The major forms of semiconduct ding order of present economic importance are 1. Dynamic Random-Access Memories(DRAMs) 2. Static Random-Access Memories(SRAMs) 3. Nonvolatile Programmable Memories(PROMs, EEPROMS, EAROMS, EPROMs) 4. Read-Only Memories(ROMs) DRAMs and SRAMs differ little in their applications. DRAMs are distinguished from SRAMs in that no bistable electronic circuit internal to the storage cell maintains the information. Instead DRAM information is stored"dynamically"as charge on a capacitor. All modern designs feature one field-effect transistor(FET)to access the information for both reading and writing and a thin film capacitor for information storage. SRAMs maintain their bistability, so long as power is applied, by a cross-coupled pair of inverters within each storage cell. Almost always two additional transistors serve to access the internal nodes for reading and writing. Most modern cell designs are CMOS, with two P-channel and four N-channel FETs Programmable memories operate much like read-only memories with the important attribute that they can be programmed at least once, and some can be reprogrammed a million times or more. Storage is almost always by means of a floating-gate FET. Information in such storage cells is not indefinitely nonvolatile. The discharge time constant is on the order of ten years. ROMs are generally programmed by a custom information mask within the fabrication sequence. As the name implies, information thence can only be read. The inf thus stored is truly nonvolatile, even when power is removed. This is the most dense form of semiconductor storage(and the least flexible). Other forms of semiconductor memories, such as associative memories and arge-coupled devices, are used rarely. c 2000 by CRC Press LLC

© 2000 by CRC Press LLC 80 Memory Devices 80.1 Integrated Circuits (RAM, ROM) Dynamic RAMs (DRAMs) • Static RAMs (SRAMs) • Nonvolatile Programmable Memories • Read-Only Memories (ROMs) 80.2 Basic Disk System Architectures Basic Magnetic Disk System Architecture • Characterization of I/O Workloads • Extensions to Conventional Disk Architectures 80.3 Magnetic Tape A Brief Historical Review • Introduction • Magnetic Tape • Tape Format • Recording Modes 80.4 Magneto-Optical Disk Data Storage Preliminaries and Basic Definitions • The Optical Path • Automatic Focusing • Automatic Tracking • Thermomagnetic Recording Process • Magneto-Optical Readout • Materials of Magneto-Optical Data Storage 80.1 Integrated Circuits (RAM, ROM) W. David Pricer The major forms of semiconductor memory in descending order of present economic importance are 1. Dynamic Random-Access Memories (DRAMs) 2. Static Random-Access Memories (SRAMs) 3. Nonvolatile Programmable Memories (PROMs, EEPROMs, EAROMs, EPROMs) 4. Read-Only Memories (ROMs) DRAMs and SRAMs differ little in their applications. DRAMs are distinguished from SRAMs in that no bistable electronic circuit internal to the storage cell maintains the information. Instead DRAM information is stored “dynamically” as charge on a capacitor. All modern designs feature one field-effect transistor (FET) to access the information for both reading and writing and a thin film capacitor for information storage. SRAMs maintain their bistability, so long as power is applied, by a cross-coupled pair of inverters within each storage cell. Almost always two additional transistors serve to access the internal nodes for reading and writing. Most modern cell designs are CMOS, with two P-channel and four N-channel FETs. Programmable memories operate much like read-only memories with the important attribute that they can be programmed at least once, and some can be reprogrammed a million times or more. Storage is almost always by means of a floating-gate FET. Information in such storage cells is not indefinitely nonvolatile. The discharge time constant is on the order of ten years. ROMs are generally programmed by a custom information mask within the fabrication sequence. As the name implies, information thence can only be read. The information thus stored is truly nonvolatile, even when power is removed. This is the most dense form of semiconductor storage (and the least flexible). Other forms of semiconductor memories, such as associative memories and charge-coupled devices, are used rarely. W. David Pricer IBM Randy H. Katz University of California, Berkeley Peter A. Lee Department of Trade and Industry, London M. Mansuripur University of Arizona, Tucson

Dynamic RAMs(DRAMs The universally used storage cell circuit of one transistor and one capacitor has remained unchanged for over 20 years. The physical implementation, however, has undergone much diversity and many refinements. The innovation in physical nplementation is driven primarily by the need to maintain a nearly constant value of capacitance while the surface area of the cell has decreased. A nearly fixed value of capacitance is needed to meet two important design goals. The cell has no internal amplification. Once the information is accessed, the stored voltage is vastly attenuated by the much larger bit line capacitance(see Fig. 80. 1). The resulting signal must be kept arger than the resolution limits of the sensing amplifier. DRAMs in particular are also sensitive to a problem called soft errors. These are typically initiated by atomic events such as the incidence of a single alpha particle. An alpha particle can ourious signal of 50,000 electrons or more. All mod- FIGURE 80.1 Cell and bit line capacitance. ern dRAm designs resolve this problem by constructing the capacitor in space out of the plane of the transistors(see Fig 80.2 for examples). Placing the capacitor in space unusable for transistor fabrication has allowed great strides in DRAM density, generally at the expense of fabrication complexity. DRAM chip capacity has increased by about a factor of four every three years. RAMs are somewhat slower than SRAMs. This relationship derives directly from the smaller signal ava from DRAMs and from certain constraints put on the support circuitry by the DRAM array. DRaM Word line Capacitor dielectric layer Insulating layer Electrode 2(Cell plate Isolation Electrode-1(Storage electrode 691815kvxi:"3:的层 FIGURE 80.2 (a)Cross section of "trench capacitors"etched vertically into the semiconductor surface of a DRAM inte- grated circuit. (Courtesy of IBM. )(b)Cross section of"stacked"capacitors fabricated above the semiconductor surface of a DRAM integrated circuit. ( Source: M. Taguchi et al., "A 40-ns 64-b parallel data bus architecture, IEEE J. Solid State Circuits, voL. 26, no. 11, P. 1495. e 1991 IEEE. With permission. e 2000 by CRC Press LLC

© 2000 by CRC Press LLC Dynamic RAMs (DRAMs) The universally used storage cell circuit of one transistor and one capacitor has remained unchanged for over 20 years. The physical implementation, however, has undergone much diversity and many refinements. The innovation in physical implementation is driven primarily by the need to maintain a nearly constant value of capacitance while the surface area of the cell has decreased. A nearly fixed value of capacitance is needed to meet two important design goals. The cell has no internal amplification. Once the information is accessed, the stored voltage is vastly attenuated by the much larger bit line capacitance (see Fig. 80.1). The resulting signal must be kept larger than the resolution limits of the sensing amplifier. DRAMs in particular are also sensitive to a problem called soft errors. These are typically initiated by atomic events such as the incidence of a single alpha particle. An alpha particle can cause a spurious signal of 50,000 electrons or more. All modern DRAM designs resolve this problem by constructing the capacitor in space out of the plane of the transistors (see Fig. 80.2 for examples). Placing the capacitor in space unusable for transistor fabrication has allowed great strides in DRAM density, generally at the expense of fabrication complexity. DRAM chip capacity has increased by about a factor of four every three years. DRAMs are somewhat slower than SRAMs. This relationship derives directly from the smaller signal available from DRAMs and from certain constraints put on the support circuitry by the DRAM array. DRAMs also FIGURE 80.2 (a) Cross section of “trench capacitors” etched vertically into the semiconductor surface of a DRAM integrated circuit. (Courtesy of IBM.) (b) Cross section of “stacked” capacitors fabricated above the semiconductor surface of a DRAM integrated circuit. (Source: M. Taguchi et al., “A 40-ns 64-b parallel data bus architecture,” IEEE J. Solid State Circuits, vol. 26, no. 11, p. 1495. © 1991 IEEE. With permission.) FIGURE 80.1 Cell and bit line capacitance

THE REVOLUTION OF ELECTRONICS TECHNOLOGY he last three decades have witnessed a revo- lution in electrical and, especially, electron technology. This revolution was paced by changes in solid-state electronics that greatly expanded capabilities while at the same time ally reduced costs. The entire field of electrical en neering has grown far beyond the boundaries that characterized it just a generation ago. Electrical neers have become the creators and masters of the most pervasive technology of our time, with pro- found effects on society and on their profession The effects of the electronics revolution are com plex. For the profession, the most obvious impact has been explosive growth. The increase in the num- ber of students studying in the field continues to be dramatic and shows no signs of slowing. The elec- trical engineering community represents the largest This 64-kB random access memory chip, developed single technical group in the world, and the mem- by IBM in 1978, was one of the densest of its time. It bers of the IEEE make up the worlds largest engi- could store as many as 64,000 bits of informa neering society.( Courtesy of the IEEE Center for th tion-roughly equivalent to 1, 000 eight-letter words. History of Electrical Engineering (Photo courtesy of the IEEE Center for the History of Electrical Engineering. require periodic intervals to"refresh"lost charge from the capacitor. This charge is lost primarily across the emiconductor junctions and must be replenished every few milliseconds. The manufacturer usually supplies hese"housekeeping, " functions with on-chip circuitry. Signal detection and amplification remain a critical focus of good DRAM design. Figure 80.3 illustrates an arrangement called a"folded bit line. This design cancels many of the noise sources originating in the array and decreases circuit sensitivity to manufacturing process variations. It also achieves a high ratio of storage cells per sense amplifier. Note the presence of the dummy cells, which create a reference signal midway between one"and a"zero"for the convenience of the sense amplifier. The stored reference voltage in this case is two driven bit lines afte lls has been written Large DRAM integrated circuit chips frequently provide other features that users may find useful. access is provided between certain adjacent addresses, usually along a common word line. Some designs on-chip buffer memories, low standby power modes, or error correction circuitry. A few DRAM chips designed to mesh with the constraints of particular applications such as image support for CRT displays. Some on-chip features are effectively hidden from the user. These include redunda nt memory addresses which the maker activates by laser to improve manufacturing yield. The largest single market for DRAMs is with microprocessors in personal computers. Rapid microprocessor performance improvements have led DRAM manufacturers to offer improvements especially designed for the PC environment. Extended Data Out mode(EDO) keeps the data accessed from a DRAM valid over a longer period of the DRAM cycle. EDO mode is intended to ease the synchronization problem between a DRAM and the increasingly higher speed microprocessor. Synchronous DRAM(SDRAM)allows the rapid sequential e 2000 by CRC Press LLC

© 2000 by CRC Press LLC require periodic intervals to “refresh” lost charge from the capacitor. This charge is lost primarily across the semiconductor junctions and must be replenished every few milliseconds. The manufacturer usually supplies these “housekeeping” functions with on-chip circuitry. Signal detection and amplification remain a critical focus of good DRAM design. Figure 80.3 illustrates an arrangement called a “folded bit line.” This design cancels many of the noise sources originating in the array and decreases circuit sensitivity to manufacturing process variations. It also achieves a high ratio of storage cells per sense amplifier. Note the presence of the dummy cells, which create a reference signal midway between a “one” and a “zero” for the convenience of the sense amplifier. The stored reference voltage in this case is created by shorting two driven bit lines after one of the storage cells has been written. Large DRAM integrated circuit chips frequently provide other features that users may find useful. Faster access is provided between certain adjacent addresses, usually along a common word line. Some designs feature on-chip buffer memories, low standby power modes, or error correction circuitry. A few DRAM chips are designed to mesh with the constraints of particular applications such as image support for CRT displays. Some on-chip features are effectively hidden from the user. These may include redundant memory addresses which the maker activates by laser to improve manufacturing yield. The largest single market for DRAMs is with microprocessors in personal computers. Rapid microprocessor performance improvements have led DRAM manufacturers to offer improvements especially designed for the “PC” environment. Extended Data Out mode (EDO) keeps the data accessed from a DRAM valid over a longer period of the DRAM cycle. EDO mode is intended to ease the synchronization problem between a DRAM and the increasingly higher speed microprocessor. Synchronous DRAM (SDRAM) allows the rapid sequential THE REVOLUTION OF ELECTRONICS TECHNOLOGY he last three decades have witnessed a revolution in electrical and, especially, electronics technology. This revolution was paced by changes in solid-state electronics that greatly expanded capabilities while at the same time radically reduced costs. The entire field of electrical engineering has grown far beyond the boundaries that characterized it just a generation ago. Electrical engineers have become the creators and masters of the most pervasive technology of our time, with profound effects on society and on their profession. The effects of the electronics revolution are complex. For the profession, the most obvious impact has been explosive growth. The increase in the number of students studying in the field continues to be dramatic and shows no signs of slowing. The electrical engineering community represents the largest single technical group in the world, and the members of the IEEE make up the world’s largest engineering society. (Courtesy of the IEEE Center for the History of Electrical Engineering.) This 64-kB random access memory chip, developed by IBM in 1978, was one of the densest of its time. It could store as many as 64,000 bits of information—roughly equivalent to 1,000 eight-letter words. (Photo courtesy of the IEEE Center for the History of Electrical Engineering.) T

MULTICOORDINATE DIGITAL INFORMATION STORAGE DEVICE Jay w. For rrester Patented February 28, 1956 #2,736,880 p to this time, digital data storage was generally done by encoding binary data on rotating magnetic drums or other means where data had to be stored and retrieved sequentially. This patent describes a syste whereby data could be stored and retrieved domly by a simple addressing scheme. It used tiny doughnut-shaped ferromagnetic cores with windings to magnetically polarize the material in one direction or the other. This was about one hundred times faster than rotating drums nd took up perhaps 2% of the volume. A Fig. 2 4-Kbyte core memory module would take up about 60 cubic inches and could access data in less than one millisecond. Random access mem- ory(rAm) was born. Core memory(as it has become known) was non-volatile; that is, the information would not be lost when power was cut. Modern non-volatile"flash" memory is yet again thousands of times faster and achieves data density of over 100,000 times greater than the breakthrough magnetic core memory described by Forrester.( Copyright o 1 DewRay Products, Inc. Used with permission. transfer of large blocks of data between the microprocessor and the DRAM without extensive signal"hand shaking". While SDRAMs do nothing to improve the access time to first data, they greatly improve the "band width"between microprocessor and DRAM Static RAMs(SRAMs The primary advantages of SRAMs as compared to DRAMs are high speed and ease of use. In addition, SRAMs fabricated in CMOS technology exhibit extremely low standby power. This later feature is effectively used in much portable equipment like pocket calculators. Bipolar SRAMs are generally faster but less dense than FEt versions. Figure 80.4 illustrates two cells. SRAM performance is dominated by the speed of the support circuits leading some manufacturers to design bipolar support circuits to FET arrays Bipolar designs frequently incorporate circuit consolidation unavailable in FET technology, such as the multi emitter cell shown in Fig. 80.4(a). Here one of the two lower emitters is normally forward biased, turning one inverter on and the other off for bistability. The upper emitters can be used either to extract a differential signal e 2000 by CRC Press LLC

© 2000 by CRC Press LLC transfer of large blocks of data between the microprocessor and the DRAM without extensive signal “handshaking”. While SDRAMs do nothing to improve the access time to first data, they greatly improve the “bandwidth” between microprocessor and DRAM. Static RAMs (SRAMs) The primary advantages of SRAMs as compared to DRAMs are high speed and ease of use. In addition, SRAMs fabricated in CMOS technology exhibit extremely low standby power. This later feature is effectively used in much portable equipment like pocket calculators. Bipolar SRAMs are generally faster but less dense than FET versions. Figure 80.4 illustrates two cells. SRAM performance is dominated by the speed of the support circuits, leading some manufacturers to design bipolar support circuits to FET arrays. Bipolar designs frequently incorporate circuit consolidation unavailable in FET technology, such as the multiemitter cell shown in Fig. 80.4(a). Here one of the two lower emitters is normally forward biased, turning one inverter on and the other off for bistability. The upper emitters can be used either to extract a differential signal MULTICOORDINATE DIGITAL INFORMATION STORAGE DEVICE Jay W. Forrester Patented February 28, 1956 #2,736,880 p to this time, digital data storage was generally done by encoding binary data on rotating magnetic drums or other means where data had to be stored and retrieved sequentially. This patent describes a system whereby data could be stored and retrieved randomly by a simple addressing scheme. It used tiny doughnut-shaped ferromagnetic cores with windings to magnetically polarize the material in one direction or the other. This was about one hundred times faster than rotating drums and took up perhaps 2% of the volume. A 4-Kbyte core memory module would take up about 60 cubic inches and could access data in less than one millisecond. Random access memory (RAM) was born. Core memory (as it has become known) was non-volatile; that is, the information would not be lost when power was cut. Modern non-volatile “flash” memory is yet again thousands of times faster and achieves data density of over 100,000 times greater than the breakthrough magnetic core memory described by Forrester. (Copyright © 1995, DewRay Products, Inc. Used with permission.) U

Practical SRAM designs routinely achieve access times of a few nanoseconds to a few tens of nanoseconds. Cycle time typically equals access time, and in at least one pipelined design, cycle time is actually less than access time SRAM integrated circuit chips have fewer special on-chip features than DRAM chips, primarily because no special performance enhancements are needed. By contrast, many other integrated circuit chips feature on- hip SRAMs. For example, many ASICs(application-specific integrated circuits) feature on-chip RAMs because of their low power and ease of use. k between processor and memory. Nonvolatile programmable memories A few nonvolatile memories are programmable just once. These have arrays of diodes or transistors with fuses or antifuse in series with platinum silicide, and polysilicon have all beene itanium, tungsten, successfully used as fuse technology (see Fig. 80.5 Most nonvolatile cells rely on trapped charge stored on a floa gate in an FET. These can be rewritten many times. The trapped charge is subject to very long term leakage, on the order of ten years. The number of times the cell may be rewritten is limited by pro gramming stress-induced degradation of the dielectric. Charge LIne eling or by avalanche tion from a region near the drain. Both phenomena are induced by over-voltage conditions and hence the degradation after repeated erase/write cycles. Commercially available chips typically promise 100 to 100,000 write cycles. Erasure of charge from the floating gate Word may be by tunneling or by exposure to ultraviolet light. Asperities on the polysilicon gate and silicon-rich oxide have both been shown enhance charging and discharging of the gate. The nomenclature sed is not entirely consistent throughout the industry. Ho EPROM is generally used to describe cells which are electronically written but uV erased. eeprom is used to describe cells which are electronically both written and erased. Cells are of either a two-or a one-transistor design. where two transistors are used. the second transistor is a conventional enhance- ment mode transistor(see Fig 80.6). The second transistor works FIGURE 80.5 PROM cells the disturb of unselected cells. it al constraints on the writing limits of the programmable transistor, which in one state may be depletion mode The two transistors in series then assume the threshold of the second(enhancement)transistor, or a very high threshold as determined by the programmable transistor. Some designs are so cleverly integrated that the features of the two transistors are merged Flash EEPROMs describe a family of single-transistor cell EPPROMs. Cell sizes are about half that of two- transistor EEPROMs, an important economic consideration. Care must be taken that these re not programmed into the depletion mode. An array of depletion mode cells would confound the read operation by providing multiple signal paths. Programming to enhancement only thresholds can be accomplished by a sequence of partial program and then monitor subcycles, until the threshold is brought to compliance with tion limits. Flash EEPROMs require bulk erasure of large portions of the array nvrAM is a term used to describe a sram or dram with nonvolatile circuit elements the cell is built to operate as a RAM with normal power applied On command or with power failure imminent, the EEPROM elements can be activated to capture the last state of the RAM cell. The nonvolatile information is restored to SRAM cell by normal internal cell regeneration when power is restored e 2000 by CRC Press LLC

© 2000 by CRC Press LLC Practical SRAM designs routinely achieve access times of a few nanoseconds to a few tens of nanoseconds. Cycle time typically equals access time, and in at least one pipelined design, cycle time is actually less than access time. SRAM integrated circuit chips have fewer special on-chip features than DRAM chips, primarily because no special performance enhancements are needed. By contrast, many other integrated circuit chips feature onchip SRAMs. For example, many ASICs (application-specific integrated circuits) feature on-chip RAMs because of their low power and ease of use. All modern microprocessors include one or more on-chip “cache” SRAM memories which provide a high speed link between processor and memory. Nonvolatile Programmable Memories A few nonvolatile memories are programmable just once. These have arrays of diodes or transistors with fuses or antifuses in series with each semiconductor cross point. Aluminum, titanium, tungsten, platinum silicide, and polysilicon have all been successfully used as fuse technology (see Fig. 80.5). Most nonvolatile cells rely on trapped charge stored on a floating gate in an FET. These can be rewritten many times. The trapped charge is subject to very long term leakage, on the order of ten years. The number of times the cell may be rewritten is limited by programming stress-induced degradation of the dielectric. Charge reaches the floating gate either by tunneling or by avalanche injection from a region near the drain. Both phenomena are induced by over-voltage conditions and hence the degradation after repeated erase/write cycles. Commercially available chips typically promise 100 to 100,000 write cycles. Erasure of charge from the floating gate may be by tunneling or by exposure to ultraviolet light. Asperities on the polysilicon gate and silicon-rich oxide have both been shown to enhance charging and discharging of the gate. The nomenclature used is not entirely consistent throughout the industry. However, EPROM is generally used to describe cells which are electronically written but UV erased. EEPROM is used to describe cells which are electronically both written and erased. Cells are of either a two- or a one-transistor design. Where two transistors are used, the second transistor is a conventional enhancement mode transistor (see Fig. 80.6). The second transistor works to minimize the disturb of unselected cells. It also removes some constraints on the writing limits of the programmable transistor, which in one state may be depletion mode. The two transistors in series then assume the threshold of the second (enhancement) transistor, or a very high threshold as determined by the programmable transistor. Some designs are so cleverly integrated that the features of the two transistors are merged. Flash EEPROMs describe a family of single-transistor cell EPPROMs. Cell sizes are about half that of twotransistor EEPROMs, an important economic consideration. Care must be taken that these cells are not programmed into the depletion mode. An array of depletion mode cells would confound the read operation by providing multiple signal paths. Programming to enhancement only thresholds can be accomplished by a sequence of partial program and then monitor subcycles, until the threshold is brought to compliance with specification limits. Flash EEPROMs require bulk erasure of large portions of the array. NVRAM is a term used to describe a SRAM or DRAM with nonvolatile circuit elements. The cell is built to operate as a RAM with normal power applied. On command or with power failure imminent, the EEPROM elements can be activated to capture the last state of the RAM cell. The nonvolatile information is restored to a SRAM cell by normal internal cell regeneration when power is restored. FIGURE 80.5 PROM cells

D. Frohmann-Bentchkowsky, "A fully decoded 2048 bit electronically programmable MOS-ROM, Digest of Technical Papers ISSCC, vol. 14, 1971 L. A Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI Circuits, Reading, Mass. Addison-Wesle 1985 F Masuoka, Are you ready of the next generation dynamic RAM chips, IEEE Spectrum Magazine, vol. 27, no 19 R. D. Pashley and S. K. Lai, Flash memories: The best of two worlds, " IEEE Spectrum Magazine, vol 26,no 12,1989. 2 Basic disk System Architectures Randy h. Katz Architects of high-performance computers have long been forced to acknowledge the existence of a large gap between the speed of the CPU and the speed of its attached I/O devices. A number of techniques have been developed in an attempt to narrow this gap, and we shall review them in this chapter key measure of magnetic disk technology is the growth in the maximum number of bits that can be stored per square inch, i. e, the bits per inch in a disk track times the number of tracks per inch of media. Called MAD, for maximal areal density, the"First Law in Disk Density " predicts [Frank, 1987 MAD=10car-1971)/10 (80.1) This is plotted against several real disk products in Fig. 80. 10. Magnetic disk technology has doubled capacity and halved price every three years, in line with the growth rate of semiconductor memory. Between 1967 and 1979 the growth in disk capacity of the average IBM data processing system more than kept up with its growth in main memory, maintaining a ratio of 1000: 1 between disk capacity and physical memory size [Stevens, 1981 In contrast to primary memory technologies, the performance of conventional magnetic disks has improved only modestly. These mechanical devices, the elements of which are described in more detail in the next section, are dominated by seek and rotation delays: from 1971 to 1981, the raw seek time for a high-end IBM disk improved by only a factor of two while the rotation time did not change[ Harker et al., 1981]. Greater recording density translates into a higher transfer rate once the information is located, and extra positioning actuators for the read/write heads can reduce the average seek time, but the raw seek time only improved at a rate of 7% per year. This is to be compared to a doubling in processor power every year, a doubling in memory density every two years, and a doubling in disk density every three years. The gap between processor performance and disk speeds continues to widen, and there is no reason to expect a radical improvement in raw disk performance in the near future To maintain balance, computer systems have been using even larger main memories or solid-state disks to buffer some of the I/O activity. This may be an acceptable solution for applications whose I/O activity has locality of reference and for which volatility is not an issue, but applications dominated by a high rate of random massive amounts of data(e.g, supercomputer applications) face a serious performance limition requests for requests for small pieces of data(e. g, transaction processing)or by a small number of sequential he rest of the chapter is organized as follows. In the next section n,we will briefly review the fundamentals of disk system architecture. The third section describes the characteristics of the applications that demand high I/O system performance. Conventional ways to improve disk performance are discussed in the last section. Basic Magnetic Disk System Architecture We will review here the basic terminology of magnetic disk devices and controllers and then examine the disk absystems of three manufacturers(IBM, Cray, and DEC). Throughout this section we are concerned with technologies that support random access, rather than sequential access(e.g, magnetic tape). A more detailed scussion, focusing on the structure of small dimension ives, can be found in Vasudeva [1988. The basic concepts are illustrated in Fig. 80. 11. A spindle consists of a collection of platters. Platters are metal disks e 2000 by CRC Press LLC

© 2000 by CRC Press LLC D. Frohmann-Bentchkowsky, “A fully decoded 2048 bit electronically programmable MOS-ROM,” Digest of Technical Papers ISSCC, vol. 14, 1971. L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI Circuits, Reading, Mass.: Addison-Wesley, 1985. F. Masuoka, “Are you ready of the next generation dynamic RAM chips,” IEEE Spectrum Magazine, vol. 27, no. 11, 1990. R. D. Pashley and S. K. Lai, “Flash memories: The best of two worlds,” IEEE Spectrum Magazine, vol. 26, no. 12, 1989. 80.2 Basic Disk System Architectures Randy H. Katz Architects of high-performance computers have long been forced to acknowledge the existence of a large gap between the speed of the CPU and the speed of its attached I/O devices. A number of techniques have been developed in an attempt to narrow this gap, and we shall review them in this chapter. A key measure of magnetic disk technology is the growth in the maximum number of bits that can be stored per square inch, i.e., the bits per inch in a disk track times the number of tracks per inch of media. Called MAD, for maximal areal density, the “First Law in Disk Density” predicts [Frank, 1987]: MAD = 10(Year-1971)/10 (80.1) This is plotted against several real disk products in Fig. 80.10. Magnetic disk technology has doubled capacity and halved price every three years, in line with the growth rate of semiconductor memory. Between 1967 and 1979 the growth in disk capacity of the average IBM data processing system more than kept up with its growth in main memory, maintaining a ratio of 1000:1 between disk capacity and physical memory size [Stevens, 1981]. In contrast to primary memory technologies, the performance of conventional magnetic disks has improved only modestly. These mechanical devices, the elements of which are described in more detail in the next section, are dominated by seek and rotation delays: from 1971 to 1981, the raw seek time for a high-end IBM disk improved by only a factor of two while the rotation time did not change [Harker et al., 1981]. Greater recording density translates into a higher transfer rate once the information is located, and extra positioning actuators for the read/write heads can reduce the average seek time, but the raw seek time only improved at a rate of 7% per year. This is to be compared to a doubling in processor power every year, a doubling in memory density every two years, and a doubling in disk density every three years. The gap between processor performance and disk speeds continues to widen, and there is no reason to expect a radical improvement in raw disk performance in the near future. To maintain balance, computer systems have been using even larger main memories or solid-state disks to buffer some of the I/O activity. This may be an acceptable solution for applications whose I/O activity has locality of reference and for which volatility is not an issue, but applications dominated by a high rate of random requests for small pieces of data (e.g., transaction processing) or by a small number of sequential requests for massive amounts of data (e.g., supercomputer applications) face a serious performance limitation. The rest of the chapter is organized as follows. In the next section, we will briefly review the fundamentals of disk system architecture. The third section describes the characteristics of the applications that demand high I/O system performance. Conventional ways to improve disk performance are discussed in the last section. Basic Magnetic Disk System Architecture We will review here the basic terminology of magnetic disk devices and controllers and then examine the disk subsystems of three manufacturers (IBM, Cray, and DEC). Throughout this section we are concerned with technologies that support random access, rather than sequential access (e.g., magnetic tape). A more detailed discussion, focusing on the structure of small dimension disk drives, can be found in Vasudeva [1988]. The basic concepts are illustrated in Fig. 80.11. A spindle consists of a collection of platters. Platters are metal disks