TABLE 25.1(cor d) Overall roadma ap Technology Characterist Year of First DRAM Shipment/Minimum Feature (um) 995/0.351998/0.252001/0.182004/0.132007/0.102010/0.07 ASIC 1100 Max number wiring levels (log On-chi 4-5 Electrical defect density(d/m) 240 Minimum mask count Cycle time days(theoretical) Maximum substrate diameter(mm) Bulk or epitaxial or SOI wafer 300 Power supply voltage (v) 25 1.8 l8-2.50.9-1.80.9 Maximum power High performance with heatsink (W) Logic without heatsink(w Design and test Volume tester cost/pi 3. 1.3 0.4 Number of test vector 16-32 16-32 IC function with Related Topics Further information The NTRS is available from the SIA, 181 Metro Drive, Suite 450, San Jose, CA 95110, telephone 408-436-6600, fax 408-436-6646.ThedocumentcanalsobeaccessedviatheSemAteChhomepageat<http://www.sematech.org> Information concerning the IC life cycle can be found in Larrabee, G. B and Chatterjee, P"DRAM Manu facturing in the 90s--Part 1: The History Lesson"and"Part 2: The Roadmap, "Semiconductor International Pp.8492,May1991 25.2 Layout, Placement, and routing Mehdi r. Zargham and Spyros tragoudas Very large scale integrated(VLSI)electronics presents a challenge, not only to those involved in the development of fabrication technology, but also to computer scientists, computer engineers, and electrical engineers. The ways in which digital systems are structured, the procedures used to design them, the trade-offs between hardware and software, and the design of computational algorithms will all be greatly affected by the coming hanges in integrated electronics A VLSI chip can today contain millions of transistors and is expected to contain more than 100 million transistors in the year 2000. One of the main factors contributing to this increase is the effort that has been invested in the development of computer-aided design( CAD) systems for VLSI design. The VLSI CAD systems are able to simplify the design process by hiding the low-level circuit theory and device physics details from the designer, and allowing him or her to concentrate on the functionality of the design and on ways of optimizing it. A VLSI CAD system supports descriptions of hardware at many levels of abstraction, such as system, absystem, register, gate, circuit, and layout levels. It allows designers to design a hardware device at an abstract level and progressively work down to the layout level. A layout is a complete geometric representation(a set of rectangles) from which the latest fabrication technologies directly produce reliable, working chips. A VLSI c 2000 by CRC Press LLC© 2000 by CRC Press LLC Related Topics 1.1 Resistors • 23.1 Processes Further Information The NTRS is available from the SIA, 181 Metro Drive, Suite 450, San Jose, CA 95110, telephone 408-436-6600, fax 408-436-6646. The document can also be accessed via the SEMATECH home page at <http://www.sematech.org>. Information concerning the IC life cycle can be found in Larrabee, G. B. and Chatterjee, P. “DRAM Manu￾facturing in the 90’s — Part 1: The History Lesson” and “Part 2: The Roadmap,” Semiconductor International, pp. 84–92, May 1991. 25.2 Layout, Placement, and Routing Mehdi R. Zargham and Spyros Tragoudas Very large scale integrated (VLSI) electronics presents a challenge, not only to those involved in the development of fabrication technology, but also to computer scientists, computer engineers, and electrical engineers. The ways in which digital systems are structured, the procedures used to design them, the trade-offs between hardware and software, and the design of computational algorithms will all be greatly affected by the coming changes in integrated electronics. A VLSI chip can today contain millions of transistors and is expected to contain more than 100 million transistors in the year 2000. One of the main factors contributing to this increase is the effort that has been invested in the development of computer-aided design (CAD) systems for VLSI design. The VLSI CAD systems are able to simplify the design process by hiding the low-level circuit theory and device physics details from the designer, and allowing him or her to concentrate on the functionality of the design and on ways of optimizing it. A VLSI CAD system supports descriptions of hardware at many levels of abstraction, such as system, subsystem, register, gate, circuit, and layout levels. It allows designers to design a hardware device at an abstract level and progressively work down to the layout level. A layout is a complete geometric representation (a set of rectangles) from which the latest fabrication technologies directly produce reliable, working chips. A VLSI ASIC 450 660 750 900 1100 1400 Max number wiring levels (logic) On-chip 4–5 5 5–6 6 6–7 7–8 Electrical defect density (d/m2 ) 240 160 140 120 100 25 Minimum mask count 18 20 20 22 22 24 Cycle time days (theoretical) 9 10 10 11 11 12 Maximum substrate diameter (mm) Bulk or epitaxial or SOI wafer 200 200 300 300 400 400 Power supply voltage (V) Desktop 3.3 2.5 1.8 1.5 1.2 0.9 Battery 2.5 1.8–2.5 0.9–1.8 0.9 0.9 0.9 Maximum power High performance with heatsink (W) 80 100 120 140 160 180 Logic without heatsink (W) 5 7 10 10 10 10 Battery (W) 2.5 2.5 3.0 3.5 4.0 4.5 Design and test Volume tester cost/pin ($K) 3.3 1.7 1.3 0.7 0.5 0.4 Number of test vectors (mP/M) 16–32 16–32 16–32 8–16 4–8 4 % IC function with BIST/DFT 25 40 50 70 90 90+ TABLE 25.1 (continued) Overall Roadmap Technology Characteristics Year of First DRAM Shipment/Minimum Feature (mm) 1995/0.35 1998/0.25 2001/0.18 2004/0.13 2007/0.10 2010/0.07