n-diffusion p-diffusion metal metal-2 FIGURE 25.4 Different layers. CAD system also supports verification, synthesis, and testing of the design. Using a CAD system, the designer can make sure that all of the parts work before actually implementing the design A variety of VLSI CAD systems are commercially available that perform all or some of the levels of abstraction of design. Most of these systems support a layout editor for designing a circuit layout. A layout-editor is software that provides commands for drawing lines and boxes, copying objects, moving objects, erasing unwanted objects, and so on. The output of such an editor is a design file that describes the layout. Usually, the design file is represented in a standard format, called Caltech Intermediate Form(CIF), which is accepted by the fabrication industr What Is layout? For a specific circuit, a layout specifies the position and dimension of the different layers of materials as they would be laid on the silicon wafer. However, the layout description is only a symbolic representation, which implifies the description of the actual fabrication process. For example, the layout representation does not explicitly indicate the thickness of the layers, thickness of oxide coating, amount of ionization in the transistors channels, etc., but these factors are implicitly understood in the fabrication process. Some of the main layers used in any layout description are n-diffusion, p-diffusion, poly, metal-l, and metal-2. Each of these layers is represented by a polygon of a particular color or pattern. As an example, Fig 25.4 presents a specific pattern for each layer that will be used through the rest of this section. As is shown in Fig. 25.5, an n-diffusion layer crossing a poly layer implies an nMOS transistor, and a P-diffusion crossing poly implies a pMOS transistor. Note that the widths of diffusion and poly are represented with a scalable parameter called lambda. These measurements, referred to as design rules, are introduced to prevent errors on the chip, such as preventing thin lines from opening(disconnecting)and short circuiting p-diffusion (before fabrication) (before fabrication) silicon oxide D-diffusion n-diffusion cross-sectional view arte (after fabrication) 9 -nMos transistor b- pMOS transistor FIGURE 25.5 Layout and fabrication of MOS transistors. c 2000 by CRC Press LLC© 2000 by CRC Press LLC CAD system also supports verification, synthesis, and testing of the design. Using a CAD system, the designer can make sure that all of the parts work before actually implementing the design. A variety of VLSI CAD systems are commercially available that perform all or some of the levels of abstraction of design. Most of these systems support a layout editor for designing a circuit layout.A layout-editor is software that provides commands for drawing lines and boxes, copying objects, moving objects, erasing unwanted objects, and so on. The output of such an editor is a design file that describes the layout. Usually, the design file is represented in a standard format, called Caltech Intermediate Form (CIF), which is accepted by the fabrication industry. What Is Layout? For a specific circuit, a layout specifies the position and dimension of the different layers of materials as they would be laid on the silicon wafer. However, the layout description is only a symbolic representation, which simplifies the description of the actual fabrication process. For example, the layout representation does not explicitly indicate the thickness of the layers, thickness of oxide coating, amount of ionization in the transistors channels, etc., but these factors are implicitly understood in the fabrication process. Some of the main layers used in any layout description are n-diffusion, p-diffusion, poly, metal-1, and metal-2. Each of these layers is represented by a polygon of a particular color or pattern. As an example, Fig. 25.4 presents a specific pattern for each layer that will be used through the rest of this section. As is shown in Fig. 25.5, an n-diffusion layer crossing a poly layer implies an nMOS transistor, and a p-diffusion crossing poly implies a pMOS transistor. Note that the widths of diffusion and poly are represented with a scalable parameter called lambda. These measurements, referred to as design rules, are introduced to prevent errors on the chip, such as preventing thin lines from opening (disconnecting) and short circuiting. FIGURE 25.4 Different layers. FIGURE 25.5 Layout and fabrication of MOS transistors