tionally and for de characteristics,pulse parametric or The functional-testing end of a computer-operated IC dynamic testing is performed chiefly on fast transistor- test system is diagrammed in Fig.3.In this system transistor logic (TTL)or emitter-coupled logic (ECL) (Teradyne's J283 "SLOT"system),each pin of the IC devices. under test is connected to a module that contains two It is important to note that these three types of tests- pairs of programmable"drivers"and a pair of compara- functional,dc parametric,and pulse parametric-are tors.The drivers are actually fast solid-state switches related to distinctly different properties of an IC,and that gate power from buffered digital-to-analog (D/A) that a test sequence of one type only,no matter how voltage sources.The voltage levels from these sources thorough,cannot provide adequate device characteriza- are assigned by computer control,and it is the function tion. of the drivers to switch these voltages into the circuit Functional testing.A digital IC responds to a combina- quickly while preserving waveform integrity.All four tion of high and low inputs (I's and 0's)by producing drivers have programmable current limiting to prevent a certain combination of high and low outputs.Func- device damage. tional testing ensures that the combinations are as they The two comparators receive programmable reference should be for the logic in question.For combinatorial voltages from the buffered source for use in determining devices in which there are relatively few inputs,one can whether IC output levels are above or below specified achieve thorough functional testing through the brute- limits.Note that during functional testing each pin is force approach of exercising all input combinations. always connected to both the driver and detector sec- This approach breaks down,however,when the IC tions of the module,and that only a software command under test contains sequential logic,where the outputs is needed to change a given channel from an input to an are a function not only of the input combination but output or vice versa,an important consideration in the also of the order in which the various inputs are ex- testing of certain ICs having pins that serve both func- ercised. tions.This arrangement also makes it possible for the The presence of sequential logic raises the number of system to apply a programmable load to an output pin possible input combinations and sequences far beyond during testing. the practical reach of even the fastest testers,and the The output of either comparator is observed or not testing problem then becomes one of choosing the best of depending on the presence or absence of a "relevance" the available compromises. software command.Thus,where one wishes to exercise One compromise approach is based on the application an IC but ignore the logic outputs (as,for example,when of random patterns to the inputs and the statistical prob- preconditioning an IC),the comparator output is simply ability that these will test the device adequately.The made nonrelevant.Where it is relevant,the system may shortcomings of this approach are that (1)the chances of be programmed to look for failures in any of three ways testing for every possible failure mode are extremely re- It can look at each pin ("nth result"),sending pass-fail mote,(2)a random pattern makes no allowance for time information back to the computer.Usually,however, delays that flip-flops or other sequential devices may it is not necessary to isolate failures down to pins and it is require at various points in their operation,and (3) sufficient to know that some pin failed at a given point the random pattern does not take into account the neces- in the test sequence.Thus all the nth-result indications sity for "initializing"certain ICs-that is,setting them can be logically oRed to give a "present result."When to some known state before testing can begin. long test patterns are applied even this method (which Alternatively,one can algorithmically generate test requires communication with the computer at each step) patterns designed to detect all the failure modes intrinsic is impractical.In such cases the "present result"indica- to the logic at hand.Software can be developed that tion is automatically strobed into the"cumulative result" will iteratively apply patterns,verify that given failure memory after each logic sentence.The cumulative result modes are or are not detected,and modify the patterns tells the operator that the IC failed somewhere along the accordingly.This is a complex process and one on which line,which is very often the only information that is of much effort is being spent.Commercial pattern-genera- interest. tion services have sprung up in recent years to satisfy the Clock-rate testing.MOS clock-rate testing is ana- growing demand for solutions to the testing problems logous to functional testing,with one important differ- associated with large-scale integration. ence:In bipolar functional testing,the test speed is very In the never-ending search for right combinations of slow compared with the maximum speed at which the IC I's and 0's,it is all too easy to overlook the fact that an will operate,and thus is not a consideration.Clock-rate IC under test sees not 1's and 0's,but fast transitions MOS testing,on the other hand,is conducted near the of voltage or current.These transitions have to be fast maximum frequency of the device,which,for today's enough to simulate the inputs the device will encounter faster devices,is in the region around 5 MHz,with 10 in its end use and to represent decisive changes of state MHz over the not-too-distant horizon.At the other end (i.e.,a transition should not be so slow as to linger in of the spectrum,measurement of the "stay-alive"time the turn-on region of a device),but they should not be so (or minimum operating frequency)of the device may fast as to produce unacceptable overshoot,ringing,or require a test frequency as low as 1 Hz. crosstalk,which can result in double-clocking of devices, Not only must the MOS test system be able to supply channel interference problems,etc.An oscilloscope high-frequency test signals,it also must supply several connected to the test points of a wafer prober will sets of them (phases),each precisely settable with respect speak volumes about an IC test system's ability to test to the others.The number of phases needed depends on ICs reliably.Unless one can take a clean test signal the types of devices to be tested;common requirements for granted,he can never be confident of his test results, are for two or four phases with a phase resolution of 1 ns no matter how elegant the test patterns. or better.The ability to manipulate phases with respect to Van Veen-An introduction to IC testing 31tionally and for dc characteristics, pulse parametric or The functional-testing end of a computer-operated IC dynamic testing is performed chiefly on fast transistor- test system is diagrammed in Fig. 3. In this system transistor logic (TTL) or emitter-coupled logic (ECL) (Teradyne's J283 "SLOT" system), each pin of the IC devices. under test is connected to a module that contains two It is important to note that these three types of tests- pairs of programmable "drivers" and a pair of compara￾functional, dc parametric, and pulse parametric-are tors. The drivers are actually fast solid-state switches related to distinctly different properties of an IC, and that gate power from buffered digital-to-analog (D/A) that a test sequence of one type only, no matter how voltage sources. The voltage levels from these sources thorough, cannot provide adequate device characteriza- are assigned by computer control, and it is the function tion. of the drivers to switch these voltages into the circuit Functional testing. A digital IC responds to a combina- quickly while preserving waveform integrity. All four tion of high and low inputs (l's and 0's) by producing drivers have programmable current limiting to prevent a certain combination of high and low outputs. Func- device damage. tional testing ensures that the combinations are as they The two comparators receive programmable reference should be for the logic in question. For combinatorial voltages from the buffered source for use in determining devices in which there are relatively few inputs, one can whether IC output levels are above or below specified achieve thorough functional testing through the brute- limits. Note that during functional testing each pin is force approach of exercising all input combinations. always connected to both the driver and detector sec￾This approach breaks down, however, when the IC tions of the module, and that only a software command under test contains sequential logic, where the outputs is needed to change a given channel from an input to an are a function not only of the input combination but output or vice versa, an important consideration in the also of the order in which the various inputs are ex- testing of certain ICs having pins that serve both func￾ercised. tions. This arrangement also makes it possible for the The presence of sequential logic raises the number of system to apply a programmable load to an output pin possible input combinations and sequences far beyond during testing. the practical reach of even the fastest testers, and the The output of either comparator is observed or not, testing problem then becomes one of choosing the best of depending on the presence or absence of a "relevance" the available compromises. software command. Thus, where one wishes to exercise One compromise approach is based on the application an IC but ignore the logic outputs (as, for example, when of random patterns to the inputs and the statistical prob- preconditioning an IC), the comparator output is simply ability that these will test the device adequately. The made nonrelevant. Where it is relevant, the system may shortcomings of this approach are that (1) the chances of be programmed to look for failures in any of three ways. testing for every possible failure mode are extremely re- It can look at each pin ("nth result"), sending pass-fail mote, (2) a random pattern makes no allowance for time information back to the computer. Usually, however, delays that flip-flops or other sequential devices may it is not necessary to isolate failures down to pins and it is require at various points in their operation, and (3) sufficient to know that some pin failed at a given point the random pattern does not take into account the neces- in the test sequence. Thus all the nth-result indications sity for "initializing" certain ICs-that is, setting them can be logically oRed to give a "present result." When to some known state before testing can begin. long test patterns are applied even this method (which Alternatively, one can algorithmically generate test requires communication with the computer at each step) patterns designed to detect all the failure modes intrinsic is impractical. In such cases the "present result" indica￾to the logic at hand. Software can be developed that tion is automatically strobed into the "cumulative result" will iteratively apply patterns, verify that given failure memory after each logic sentence. The cumulative result modes are or are not detected, and modify the patterns tells the operator that the IC failed somewhere along the accordingly. This is a complex process and one on which line, which is very often the only information that is of much effort is being spent. Commercial pattern-genera- interest. tion services have sprung up in recent years to satisfy the Clock-rate testing. MOS clock-rate testing is ana￾growing demand for solutions to the testing problems logous to functional testing, with one important differ￾associated with large-scale integration. ence: In bipolar functional testing, the test speed is very In the never-ending search for right combinations of slow compared with the maximum speed at which the IC l's and 0's, it is all too easy to overlook the fact that an will operate, and thus is not a consideration. Clock-rate IC under test sees not l's and 0's, but fast transitions MOS testing, on the other hand, is conducted near the of voltage or current. These transitions have to be fast maximum frequency of the device, which, for today's enough to simulate the inputs the device will encounter faster devices, is in the region around 5 MHz, with 10 in its end use and to represent decisive changes of state MHz over the not-too-distant horizon. At the other end (i.e., a transition should not be so slow as to linger in of the spectrum, measurement of the "stay-alive" time the turn-on region of a device), but they should not be so (or minimum operating frequency) of the device may fast as to produce unacceptable overshoot, ringing, or require a test frequency as low as 1 Hz. crosstalk, which can result in double-clocking of devices, Not only must the MOS test system be able to supply channel interference problems, etc. An oscilloscope high-frequency test signals, it also must supply several connected to the test points of a wafer prober will sets of them (phases), each precisely settable with respect speak volumes about an IC test system's ability to test to the others. The number of phases needed depends on ICs reliably. Unless one can take a clean test signal the types of devices to be tested; common requirements for granted, he can never be confident of his test results, are for two or four phases with a phase resolution of 1 ns no matter how elegant the test patterns. or better. The ability to manipulate phases with respect to Van Veen-An introduction to IC testing 31