四、运算器设计 例2:设计8位整数加法器 LIBRARY IEEE USE IEEE STD LOGIC 1164.ALL: USE IEEESTD LOGIC ARITH.ALL; ENTITY ifg 8 IS PORTO opl, op2: IN UNSIGNED(3 DOWNTO0); result: OUT INTEGER); END ifg aRChitECtURE behavior oF ifg IS BEGIN 将数据 result<=CONV INTEGER(OPI+OP2); 类型转 END behavior; 换为 致例2：设计8位整数加法器 将数据 类型转 换为一 致 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY jfq8 IS PORT( op1,op2: IN UNSIGNED(3 DOWNTO 0); result: OUT INTEGER); END jfq8; ARCHITECTURE behavior OF jfq8 IS BEGIN result<=CONV_INTEGER(OP1+OP2); END behavior; 四、运算器设计