四、运算器设计 例1:设计4位二进制加法器 LIBRARY IEEE: USE IEEESTD LOGIC 1164.ALLS USE IEEE STD LOGIC ARITHALL USE IEEE STD LOGIC UNSIGNEDALL: ENTITY ifq Is PORT a, b: IN STD LOGIC VECOR(3 DOWNTOO sum: OUTSTD LOGIC VECTOR(4 DOWNTOO) END jfq4: aRChITECTURE behavior oF ifg Is BEGIN 数据类 PROCESS(a, b) BEGIN 型必须 sum<=(0a)+(0&b); 致才 END PROCESS 能赋值 eNd behavior四、运算器设计 例1：设计4位二进制加法器 数据类 型必须 一致才 能赋值 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY jfq4 IS PORT( a,b: IN STD_LOGIC_VECOR(3 DOWNTO 0); sum: OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); END jfq4; ARCHITECTURE behavior OF jfq4 IS BEGIN PROCESS(a,b) BEGIN sum<=(‘0’&a)+(‘0’&b); END PROCESS; END behavior;