Often the boundary scan TAP controller is re-used to P1P2-P可X RPCT Cell manage other internal test modes and test logic such as memory BIST and logic BIST.These tests can be easily re- used and controlled at board and higher levels of integration BC_1Cell through the boundary scan TAP Scan_In 1 scan out 1 VII LOW PIN COUNT TEST sign co Even though ICs of have many device IO pins.there are many advantages to reducing the tester interface to very few TDI pins.When the tester interface requires just a few pins then it TAP Scen and is possible to test several devices in parallel -multisite TestKompress P01P02..=P0X testing.Multisite testing is very popular for IC test since it is a great efficiency improvement. Figure 6.Low pin count test interface for IC testing Using a traditional scan strategy distributes the scan cells between the scan chains.Thus,the more scan chains the VIII.DIAGNOSING TEST FAILURES shorter they are and the fewer cycles to load them.If the scan chains are reduced to simplify the tester interface then they IC fabrication sites take advantage of the huge amount of will be longer in length and the test cycles and test time will controllability and observability available through scan be longer.Logic BIST solves this problem by not needing a technology.The algorithms in scan ATPG tools can process tester interface other than to initiate the test and check the scan tester failures and reverse engineer the results to final status.Though there are some test quality limitations determine the source of the failure.Scan diagnostics tools with logic BIST since it randomly targets faults.For testing have been developed to the point that they not only can report specific paths or other deterministic faults,deterministic the defective internal gate port or interconnect but also can ATPG may be desired. show the location in the physical silicon.In addition,the Fortunately,the embedded compression techniques such diagnostics ATPG tools can often determine the type of as EDT [3]can use as few as one tester scan channel but still defect that occurred in the silicon such as bridge between apply the tests much faster and in fewer tester cycles than nets,opens,and more. traditional scan.This is possible due to the technique including many short internal scan chains and transforming compressed data to the necessary scan cells during pattern IX TAKING ADVANTAGE OF IC TEST FEATURES loads.Some studies show that reducing a traditional scan approach from 32 scan chains to one embedded compression IC test continues to evolve but is generally at a very channel at the same time reduces the test cycles and test time mature state with reliable and high quality parts being by 8x [5].The IC IO pins do not need to be directly delivered after testing.DPM rates of only 100 or less are contacted by the tester because the boundary scan cells are possible with the existing test methods.Structured DFT such converted into scan chains during a special reduced pin count as scan technology breaks down the complexity of an IC into test(RPCT)mode [4]. smaller easier to test components.Even techniques to reduce The LPCT strategy can be controlled by a few pins as test application time and the tester interface exist and are well shown in the figure below or controlled completely through understood.There is a potential to take advantage of these IC the standard boundary scan TAP interface.Thus,higher test methods and apply similar strategies to higher levels of levels of assembly have the potential to perform detailed integration. device testing through a standard interface. REFERENCES [1]M.Beck,et.,al.,Logic Design for On-Chip Test Clock Generation- Implementation Details and Impact on Delay Test Quality",DATE 2005. [2☒] Boyer J,et al.,"Reducing The Design Impact Of DFT In The Nanometer Era",Electronic Design,Oct 2006. [3]J.Rajski,et al.,"Embedded Deterministic Test for Low Cost Manufacturing Test,"Proc.Int'l Test Conf.(ITC 02),IEEE Press, 2002,Pp.301-310. [4]J.Jahangiri,et al.,"Achieving High Test Quality with Reduced Pin Count Testing,"ATS 2005. [5]R.Press,"High Quality Test with Minimal Pins,"EDA Tech Forum Magazine,March 2008.Often the boundary scan TAP controller is re-used to manage other internal test modes and test logic such as memory BIST and logic BIST. These tests can be easily re￾used and controlled at board and higher levels of integration through the boundary scan TAP. VII. LOW PIN COUNT TEST Even though ICs of have many device IO pins, there are many advantages to reducing the tester interface to very few pins. When the tester interface requires just a few pins then it is possible to test several devices in parallel – multisite testing. Multisite testing is very popular for IC test since it is a great efficiency improvement. Using a traditional scan strategy distributes the scan cells between the scan chains. Thus, the more scan chains the shorter they are and the fewer cycles to load them. If the scan chains are reduced to simplify the tester interface then they will be longer in length and the test cycles and test time will be longer. Logic BIST solves this problem by not needing a tester interface other than to initiate the test and check the final status. Though there are some test quality limitations with logic BIST since it randomly targets faults. For testing specific paths or other deterministic faults, deterministic ATPG may be desired. Fortunately, the embedded compression techniques such as EDT [3] can use as few as one tester scan channel but still apply the tests much faster and in fewer tester cycles than traditional scan. This is possible due to the technique including many short internal scan chains and transforming compressed data to the necessary scan cells during pattern loads. Some studies show that reducing a traditional scan approach from 32 scan chains to one embedded compression channel at the same time reduces the test cycles and test time by 8x [5]. The IC IO pins do not need to be directly contacted by the tester because the boundary scan cells are converted into scan chains during a special reduced pin count test (RPCT) mode [4]. The LPCT strategy can be controlled by a few pins as shown in the figure below or controlled completely through the standard boundary scan TAP interface. Thus, higher levels of assembly have the potential to perform detailed device testing through a standard interface. Figure 6. Low pin count test interface for IC testing. VIII. DIAGNOSING TEST FAILURES IC fabrication sites take advantage of the huge amount of controllability and observability available through scan technology. The algorithms in scan ATPG tools can process scan tester failures and reverse engineer the results to determine the source of the failure. Scan diagnostics tools have been developed to the point that they not only can report the defective internal gate port or interconnect but also can show the location in the physical silicon. In addition, the diagnostics ATPG tools can often determine the type of defect that occurred in the silicon such as bridge between nets, opens, and more. IX. TAKING ADVANTAGE OF IC TEST FEATURES IC test continues to evolve but is generally at a very mature state with reliable and high quality parts being delivered after testing. DPM rates of only 100 or less are possible with the existing test methods. Structured DFT such as scan technology breaks down the complexity of an IC into smaller easier to test components. Even techniques to reduce test application time and the tester interface exist and are well understood. There is a potential to take advantage of these IC test methods and apply similar strategies to higher levels of integration. REFERENCES [1] M. Beck, et., al., ” Logic Design for On-Chip Test Clock Generation – Implementation Details and Impact on Delay Test Quality”, DATE 2005. [2] Boyer J, et al., “Reducing The Design Impact Of DFT In The Nanometer Era”, Electronic Design, Oct 2006. [3] J. Rajski, et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,” Proc. Int’l Test Conf. (ITC 02), IEEE Press, 2002, pp. 301-310. [4] J. Jahangiri, et al., “Achieving High Test Quality with Reduced Pin Count Testing,” ATS 2005. [5] R. Press, “High Quality Test with Minimal Pins,” EDA Tech Forum Magazine, March 2008