by redundancy substitution such that the memory becomes compactor operational. decompressor design core x+8++1 V.TESTING FOR SUBTLE DEFECTS scan chains Scan and memory BIST provide an excellent level of test and often can easily provide high levels of defect detection with standard pattern types.Fabrication technologies used in recent years enable more integration of gates within each IC and faster functional frequencies.Unfortunately,one side effect was that the defect distributions shifted.Traditional scan testing continues to detect most defects but the population of more subtle defects started raising the DPM levels.In particular,timing-related defects are not detected mask register with standard scan and were often responsible for one half or more of the defective parts that were escaping test. Trying to operate testers at IC frequencies could be very Figure 4.Embedded deterministic test enables high quality targeted challenging,especially for IC frequencies greater than 200 pattern but with 100x fewer tester cycles per pattem. MHz.A well adopted solution is to use the existing functional internal clock generation logic or PLLs embedded VI BOUNDARY SCAN AND HIGHER LEVEL TEST within the IC [1].Scan patterns can be loaded as normal using an external tester clock.The scan patterns include data Some IC test structures are primarily used for higher level that places the PLL clock generation logic in a mode such testing.Boundary scan technology was developed to provide that several at-speed clock pulsed can be produced internally a simple method of testing for board-level (or MCM) to capture results using functional clocks.As a result,timing manufacturing defects.A test structure is added to the IC IO defects can be detected but the resolution of the timing is pins with a controller.A four to five pin test access port internally generated.The accuracy of the clocking and test is (TAP)controls a state machine that operates the boundary independent of the tester capabilities since the internal PLL is scan test modes.Boundary scan test is similar to scan,except used [2].These at-speed scan patterns are popular today and the control and observability are via boundary scan cells several other newer types of scan patterns are gaining in placed at each of the device's functional IO.The boundary usage. scan test process consists of loading values into the boundary The growth in scan patterns has a big impact on test time scan registers,applying them to the device outputs and onto and cost.Embedded scan compression techniques were the board interconnects,capturing the responses at other developed to enable all the additional scan pattern types to be device pin inputs,and shifting out for verification.Thus,the applied but without any additional tester time or cost [3]. board level manufacturing defects can be checked without They embed additional logic between the devices IO and scan having to understand the Ic designs or propagate signals chains.This logic acts as a transform function to take tester through them.In addition,the interface to thoroughly test the data and expand it to many short internal scan chains that board is through a simple four to five pin standard port. ensure detection of targeted faults.Scan cell values that do Connecting to the various device IO signals is not necessary not contribute to detection for that pattern are loaded with Boundary scan is common on many commercial products and random values from the embedded logic instead of storing standardized as IEEE standard 1149.1. data on the tester.As a result,the tester loads and verifies values similar to normal scan test patterns but the load and unload time is fifty to one hundred times faster.The highest Chip 2 level of test quality is possible because the patterns are deterministic,specifically targeting faults,and due to the compression all the pattern types can be applied without cost TD implications.The need to apply more test patterns has driven TCK Circuit Prior to Cireui Prior to the usage of embedded compression to be more popular than Boundary Scar Boundary Scan Inse rtion traditional scan. Figure 5.Board with two devices containing boundary scanby redundancy substitution such that the memory becomes operational. V. TESTING FOR SUBTLE DEFECTS Scan and memory BIST provide an excellent level of test and often can easily provide high levels of defect detection with standard pattern types. Fabrication technologies used in recent years enable more integration of gates within each IC and faster functional frequencies. Unfortunately, one side effect was that the defect distributions shifted. Traditional scan testing continues to detect most defects but the population of more subtle defects started raising the DPM levels. In particular, timing-related defects are not detected with standard scan and were often responsible for one half or more of the defective parts that were escaping test. Trying to operate testers at IC frequencies could be very challenging, especially for IC frequencies greater than 200 MHz. A well adopted solution is to use the existing functional internal clock generation logic or PLLs embedded within the IC [1]. Scan patterns can be loaded as normal using an external tester clock. The scan patterns include data that places the PLL clock generation logic in a mode such that several at-speed clock pulsed can be produced internally to capture results using functional clocks. As a result, timing defects can be detected but the resolution of the timing is internally generated. The accuracy of the clocking and test is independent of the tester capabilities since the internal PLL is used [2]. These at-speed scan patterns are popular today and several other newer types of scan patterns are gaining in usage. The growth in scan patterns has a big impact on test time and cost. Embedded scan compression techniques were developed to enable all the additional scan pattern types to be applied but without any additional tester time or cost [3]. They embed additional logic between the devices IO and scan chains. This logic acts as a transform function to take tester data and expand it to many short internal scan chains that ensure detection of targeted faults. Scan cell values that do not contribute to detection for that pattern are loaded with random values from the embedded logic instead of storing data on the tester. As a result, the tester loads and verifies values similar to normal scan test patterns but the load and unload time is fifty to one hundred times faster. The highest level of test quality is possible because the patterns are deterministic, specifically targeting faults, and due to the compression all the pattern types can be applied without cost implications. The need to apply more test patterns has driven the usage of embedded compression to be more popular than traditional scan. Figure 4. Embedded deterministic test enables high quality targeted pattern but with 100x fewer tester cycles per pattern. VI. BOUNDARY SCAN AND HIGHER LEVEL TEST Some IC test structures are primarily used for higher level testing. Boundary scan technology was developed to provide a simple method of testing for board-level (or MCM) manufacturing defects. A test structure is added to the IC IO pins with a controller. A four to five pin test access port (TAP) controls a state machine that operates the boundary scan test modes. Boundary scan test is similar to scan, except the control and observability are via boundary scan cells placed at each of the device’s functional IO. The boundary scan test process consists of loading values into the boundary scan registers, applying them to the device outputs and onto the board interconnects, capturing the responses at other device pin inputs, and shifting out for verification. Thus, the board level manufacturing defects can be checked without having to understand the IC designs or propagate signals through them. In addition, the interface to thoroughly test the board is through a simple four to five pin standard port. Connecting to the various device IO signals is not necessary. Boundary scan is common on many commercial products and standardized as IEEE standard 1149.1. Figure 5. Board with two devices containing boundary scan