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第26卷第8期 半导体学报 Vol.26 No.8 2005年8月 CHINESE JOURNAL OF SEMICONDUCTORS Aug.,2005 A CMOS Fully Integrated Frequency Synthesizer with Stability Compensation He Jie,Tang Zhangwen,Min Hao,and Hong Zhiliang (State Key Laboratory of ASIC System,Fudan University,Shanghai 200433,China) Abstract:A complete closed-loop third-order s-domain model is analyzed for a frequency synthesizer.Based on the model and root-locus technique,the procedure for parameters design is described,and the relationship between the process,voltage,and temperature variation of parameters and the loop stability is quantitatively analyzed.A variation margin is proposed for stability compensation.Furthermore,a simple adjustable current cell in the charge pump is proposed for additional stability compensation and a novel VCO with linear gain is adopted to limit the total varia- tion.A fully integrated frequency synthesizer from 1 to 1.05GHz with 250kHz channel resolution is implemented to verify the methods. Key words:frequency synthesizer;closed-loop third-order s-domain;loop parameters;PVT variation;stability; variation margin EEACC:1205;2570D CLC number:TN4 Document code:A Article ID:0253-4177(2005)08-1524-08 rifice performance of the phase noise and spur level 1 Introduction suppression.The better methods are to use config- urable current to compensate the change of division Monolithic frequency synthesizers based on ratio[7]and nonlinearity of VCO gainC43.However, charge pump PLL (CPLL)are prevailing in mod-these methods are of some complexity and not able ern communication systems.Loop performances,to compensate for all variation factors. such as stability,phase noise (or jitter),and switc- A CPLL based frequency synthesizer is inher- hing speed,are important design criteria and dis-ently discrete-time.Fortunately,accurate z-domain cussed in many publicationsi-6.Synthesizer de-models,state space analysis[8.9),and impulse-invar- sign is a tradeoff process to derive the parameters iant transformation io],have proven that if the loop according to specifications.Unfortunately,current,bandwidth is less than 1/20 of the reference clock, resistor,and capacitor always vary with process,s-domain model predicts the same behavior as z-do- voltage,and temperature (PVT).VCO gain is al-main models.As a result,s-domain model is also ways highly nonlinear.Variation and nonlinearity suitable for a CPLL frequency synthesizer.Tradi- tend to unstabilize the loop,especially in strict con-tionally,closed-loop s-domain model is always sim- ditions.In order to have stability,one way is to sac-plified into second.8).However,the actual Project supported by the Shanghai Science &Technology Committee,China Under System-Design-Chip(SDC)Program(No.037062019)and the Shanghai AM(Applied Material)Funds(No.0425) He Jie male,was born in 1978.PhD candidate.His research interest is in integrated RF frequency synthesizer and mixed-signal design. Tang Zhangwen male,was born in 1977,assistant professor.His research interests are in LC-VCO and CMOS RF TV tuner. Min Hao male.professor,adviser of PhD candidates.His research interests are in integrated circuit design and system integration. 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