1330 半导体学报 第26卷 3.2 Depletion regions isolation where Na,Np (atoms/cm3)are the doping densi- Figures 2(a)and (b)are the cross section and ties in the p-type material and n-type material,re- spectively,e is the permittivity of the silicon,is planform of the dual pn junctions substrate isola- tion,respectively.The resistance of the pt-diffu- the built-in potential of pn junction,and Vg is the reverse bias across the junction. sion or well is less than that of the substrate.The The depletion width will increase with reverse pn junction must be made like a metal ground bias across the junction. shielding,again in order to protest the eddy cur- rent.Thus,the thickness of high resistance(THR) 3.3 Lumped-elements models is equivalent to the depth of the bottom pn junction in the substrate,as shown in Fig.2(a).Therefore, Figure 3 is the lumped-elements model of a the CMOS technology with a deep-well is a better two-port on-chip inductor for floating patterned choice for a high performance inductor with JSIS. dual pn junctions isolation and patterned ground Capacitive coupling substrate current (CCSC)and shielding structures.At the series branch of the x- eddy current(EC)in the substrate are the results network,model parameters Ls,Rs,and Cs repre- of high frequency effects and concentrate on the sent the series inductance,series resistance,and in- top of substrate.It is found that 90%of magnetic ter-turn fringing capacitance of the inductor,re- energy is dissipated within a depth of 10um below spectively.The model parameter Cm.represents the substrate surfacets.Thus,depletion layers re- coupling-capacitance between the suspended induc- duce the CCSC and EC,substrate losses are re- tor body and the substrate (where Cx is the capac- duced,and the Q factor of the inductor is im- itance of the oxide layer and C is the capacitance of proved. the pn junction).C.ub and Raub represent the capaci- With an approximation of abrupt junction,the tance and resistance of the substrate,respectively. corresponding depletion width (Wa)is given by Rros represents the resistance of the patterned 2esNA+ND√/NR+ ground-shielding layer in parallel with the sub- (3) gNAND strate. Port2 Port2 :C(1) :C(0 (a) (b) Fig.3 Lumped-elements model of a two-port on-chip inductor for floating patterned dual pn junctions isolation (a) and for patterned ground shielding structures (b) outs to calibrate the on-wafer testing wiring and 4 Experiment and discussion pads(10].On-wafer measurement of inductors is conducted using a network analyzer and cascade Inductors are fabricated in a 0.35gm two-poly microtech probe station with coplanar ground-sig- four-metal CMOS processes,as shown in Fig.4. nal-ground (GSG)probes. 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