第7期 Jian Hongyan et al.:Patterned Dual pn Junctions Restraining Substrate Loss of... 1331 therefore,L,is increased and R,is decreased,as shown in Fig.7.Thus,the maximum quality factor is increased with Vg from OV to 3V by a further ■ 19%.The frequency of the maximum Q(fMQ)and fsg of the inductor are reduced because the reduced quantity of the inductance due to eddy currents is ■41级服w出■ 。国■ decreased.From 4V Vg the depletion regions of two neighbor n-wells touch.The lateral pn junction AI dies away at 7V Vg and the THR is not only the Fig.4 Die photos of the inductors in 0.35um CMOS depth of the bottom pn junction in the substrate, processes (a)and one inductor with probes (b) but also the relatively thinner thickness of the de- isolation structure are shown in Fig.5.The space pletion of the vertical pn junction.Thus,increasing between the adjacent n-well slots is 1.Ium,which V&from 3V to 7V decreases the maximum quality is the minimum space that design rule check per- factor by a further 19%and the fMo and fsk of the mits under a 3.3V source voltage.The p-substrate inductor are increased because the reduced quantity and p diffusion layer are connected with the of the inductance due to eddy currents are in- ground while the n-well is connected with the bias creased.This phenomenon validates the theory that voltage (VR).Thus,the electric fields of the induc- the JSIS can lower the loss induced by the eddy tor are terminated at the p diffusion layer and the currents in the substrate.The capacitive coupling pn junction capacitor does not have an effect on the substrate current and eddy current in the substrate parasitical capacitance and fsg of the inductor (in are the results of high frequency effects and con- order to validate the reduced eddy current due to centrate on the top of the substrate.This result can JSIS).Ohmic loss from the eddy currents is only be safely extended to obtain the conclusion that the substrate loss.A lumped-elements model of a two- JSIS can also reduce the loss caused by the capaci- port on-chip inductor with a grounded p shielding tive coupling currents in the substrate. layer is shown in Fig.3(b). 3V 4 pi业 T下 -C 8 日 0. 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