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1332 半导体学报 第26卷 (a) (b) 1.50 4 1.45 1.40 1.35 1.30 6V 1.25 1.20 1.15 3 4 4 Frequency/GHz Frequency/GHz Fig.7 Ls and Rs of the single-end spiral inductor with PNP isolation structure solation structures for inductors consisting of alter- nating patterned dual pn junctions with voltage Acknowledgments The authors would like to controlled,variable lateral and vertical depletion thank Prof.Sun Lingling,Wen Jincai,Chen Zhanfei regions are presented.The structure covers the of the Hangzhou University of Electronic Science whole area underneath an inductor and is compati- &Technology and Prof.Li Fuxiao of the Nanjing ble with standard digital CMOS process flow.The 55th Research Institute of Information Industrial THR is not equivalent to the thickness of the de- Department for measurements. pletion regions of the vertical pn junction but the depth of the bottom pn junction in the substrate. References Applying a voltage to the structure alters depletion regions and the number of free carriers underneath [1]Burghartz J N,Rejaei B.On the design of RF spiral inductors the inductor.The THR is thus increased.The eddy on silicon.IEEE Trans Electron Devices,2003.50(3):718 current in the substrate is reduced by the depletion [2 Yue C P.Wong SS.On-chip spiral inductors with patterned of the pn junction.Therefore,the inductance is in- ground shields for SI-based RF ICs.IEEE J Solid-State Cir- cuits,1998,33(5):734 creased because the reduced quantity of the induct- [3]Yoon J B.Kim BI.Choi Y S.et al.3-D construction of mono- ance due to eddy currents is decreased.For the first lithic passive components for RF and microwave ICs using time,pn junction substrate isolation that can re- thick-metal surface micromachining technology.IEEE Trans duce the substrate loss caused by the eddy currents Microw Theory Tech.2003.51(1):279 is reliably validated.The maximum quality factor is [4]Chen T S.Deng J D S.Lee C Y.et al.Improved performance increased by 19%,which validates the theory that of Si-based spiral inductors.IEEE Microwave and Wireless Components Letters.2004.14(10):466 the pn junction isolation substrates can reduce the [5]Danesh M.Long J R.Differentially driven symmetric micros- substrate loss caused by the eddy currents and ca- trip induetors.IEEE Trans Microw Theory Tech.2002.50 pacitive coupling currents in the substrate.Dual pn (1):332 junctions substrate isolation structure and deep- [6]Kim Kihong O K.Characteristics of an integrated spiral in- well technology are better choices for a high per- ductor with an underlying n-well.IEEE Trans Electron De- formance inductor with JSIS.Using a ground p vices,1997,44:1565 diffusion layer and patterned dual pn junction with [7]Maget J,Kraus R.Tiebout M.Voltage-controlled substrate structure for integrated inductors in standard digital CMOS controlled voltage,the electric energy loss and technologies.ESSDERC,Session D15:New Device Concepts. magnetic energy loss in the substrate can be re- 2002 duced. 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