IEEE AUTOTESTCON 2008 Salt Lake City,UT,8-11 September 2008 IC design-for-test and testability features Ron Press Mentor Graphics Corporation Abstract-IC test is at a mature state where automated tools are ICs.Though,IC complexity steadily increased to the point used for DFT feature insertion and pattern generation.This paper where functional test became too impractical for most summarizes the most common digital IC design-for-test (DFT) devices.Once device integration started to include tens of techniques in use today.Most of the focus is on testing and thousands of gates,it became a challenge to know the validating the correct operation of ICs after fabrication.However. operation of the device well enough to create a functional many of the IC DFT features can also be re-used in higher level test and in the field.In addition,some of the concepts in the well known test.Even if the functional test could be manually created,it strategies used for IC testing may be also effective for higher level would be very difficult to grade the effectiveness of the test of assembly test.Some of the topics presented on include scan, and determine any logic in the device that wasn't tested. automatic test pattern generation (ATPG).boundary scan,built-in Structural test approaches were developed because self-test (BIST),memory BIST and repair,secure IC test, creating very thorough functional tests became unrealistic for diagnostics,and test challenges. many ICs.Today,it is not uncommon for us to see ICs with tens or hundreds of millions of gates within them.What was Keywords scan.ATPG.built-in self-test,BIST,IC test.LPCT. needed was a method to break down the enormous structured test. complexity of an IC into simpler functions.In particular, sequential states drive most of the complexity within an IC. I.IC TEST QUALITY REQUIREMENTS For instance,it could require thousands or tens of thousands of clock cycles to propagate one value at a primary input High quality test for ICs is extremely important for many through the IC sequential logic before a single output can be products and can have a dramatic impact on system and predicted. assembly costs.A device that goes into a two dollar musical Scan technology replaces all the sequential elements(flip greeting card may be acceptable not to test at all prior to flops or latches)with a special device called a scan cell.Scan assembly.However,a device that is assembled into a ten cells operate the same as the standard sequential device in thousand dollar circuit board has a significant impact if it is functional operation.When a scan enable (SE)signal is defective.The cost of test and cost impact of a defect driven high then the scan cells are placed into a scan test increases dramatically with each progressive level of mode and scan cells are configured into long shift registers. assembly.As a result,the IC test has become well referred to as scan chains.An example is shown in the figure understood and standardized approaches are capable of below.When SE is asserted,all sequential gates can be detecting most defects.Test quality of ICs is at the state that initialized by shifting in known values from a tester into some companies are confident that out of every one million scan_in(SI).As a result,it is very easy to set up a desired parts shipped less than 50 defective parts will escape their test initial state.Then SE can be set to zero and the circuit will be methods.Defects per million(DPM)is the common term for in a normal mode of operation.Thus,if the clock is pulsed. how many defective parts escape test out of every million all the internal values from the combinational logic will be parts shipped. captured into the sequential logic as in a normal functional Parts that are known to be well tested make the task of clock cycle.Next.SE is asserted again and all the captured higher level assembly testing much easier.Known good ICs values can be shifted out for tester verification. assembled on a board only need to be tested to verify that board level manufacturing defects didn't occur.So,instead of having to test the function of the board,many companies can just check the board interconnects and chip 10. IC manufacturers understand the impact of shipping S defective parts and the direct correlation to their profitability. an Out SE This is especially true if the IC is assembled into a mission- critical product;a defect could result in loss of life and ruin the manufacturer's reputation and business. Figure 1.Scan structure provides controllability and observability to each internal sequential element. II.SCAN TEST AND ATPG Scan test converts the functional device with typically Conceptually,it might seem logical to simply test an IC by only a few hundred primary input and output pins into an checking that it functionally operates how it was designed to extremely testable circuit.In scan mode,the IC appears as work.Functional testing was the common approach for early just combinational logic between hundreds of thousands and 978-1-4244-2226-5/08/S25.00©20081EEEIC design-for-test and testability features Ron Press Mentor Graphics Corporation Abstract – IC test is at a mature state where automated tools are used for DFT feature insertion and pattern generation. This paper summarizes the most common digital IC design-for-test (DFT) techniques in use today. Most of the focus is on testing and validating the correct operation of ICs after fabrication. However, many of the IC DFT features can also be re-used in higher level test and in the field. In addition, some of the concepts in the well known strategies used for IC testing may be also effective for higher level of assembly test. Some of the topics presented on include scan, automatic test pattern generation (ATPG), boundary scan, built-in self-test (BIST), memory BIST and repair, secure IC test, diagnostics, and test challenges. Keywords – scan, ATPG, built-in self-test, BIST, IC test, LPCT, structured test. I. IC TEST QUALITY REQUIREMENTS High quality test for ICs is extremely important for many products and can have a dramatic impact on system and assembly costs. A device that goes into a two dollar musical greeting card may be acceptable not to test at all prior to assembly. However, a device that is assembled into a ten thousand dollar circuit board has a significant impact if it is defective. The cost of test and cost impact of a defect increases dramatically with each progressive level of assembly. As a result, the IC test has become well understood and standardized approaches are capable of detecting most defects. Test quality of ICs is at the state that some companies are confident that out of every one million parts shipped less than 50 defective parts will escape their test methods. Defects per million (DPM) is the common term for how many defective parts escape test out of every million parts shipped. Parts that are known to be well tested make the task of higher level assembly testing much easier. Known good ICs assembled on a board only need to be tested to verify that board level manufacturing defects didn’t occur. So, instead of having to test the function of the board, many companies can just check the board interconnects and chip IO. IC manufacturers understand the impact of shipping defective parts and the direct correlation to their profitability. This is especially true if the IC is assembled into a mission￾critical product; a defect could result in loss of life and ruin the manufacturer’s reputation and business. II. SCAN TEST AND ATPG Conceptually, it might seem logical to simply test an IC by checking that it functionally operates how it was designed to work. Functional testing was the common approach for early ICs. Though, IC complexity steadily increased to the point where functional test became too impractical for most devices. Once device integration started to include tens of thousands of gates, it became a challenge to know the operation of the device well enough to create a functional test. Even if the functional test could be manually created, it would be very difficult to grade the effectiveness of the test and determine any logic in the device that wasn’t tested. Structural test approaches were developed because creating very thorough functional tests became unrealistic for many ICs. Today, it is not uncommon for us to see ICs with tens or hundreds of millions of gates within them. What was needed was a method to break down the enormous complexity of an IC into simpler functions. In particular, sequential states drive most of the complexity within an IC. For instance, it could require thousands or tens of thousands of clock cycles to propagate one value at a primary input through the IC sequential logic before a single output can be predicted. Scan technology replaces all the sequential elements (flip flops or latches) with a special device called a scan cell. Scan cells operate the same as the standard sequential device in functional operation. When a scan_enable (SE) signal is driven high then the scan cells are placed into a scan test mode and scan cells are configured into long shift registers, referred to as scan chains. An example is shown in the figure below. When SE is asserted, all sequential gates can be initialized by shifting in known values from a tester into scan_in (SI). As a result, it is very easy to set up a desired initial state. Then SE can be set to zero and the circuit will be in a normal mode of operation. Thus, if the clock is pulsed, all the internal values from the combinational logic will be captured into the sequential logic as in a normal functional clock cycle. Next, SE is asserted again and all the captured values can be shifted out for tester verification. Figure 1. Scan structure provides controllability and observability to each internal sequential element. Scan test converts the functional device with typically only a few hundred primary input and output pins into an extremely testable circuit. In scan mode, the IC appears as just combinational logic between hundreds of thousands and IEEE AUTOTESTCON 2008 Salt Lake City, UT, 8-11 September 2008 978-1-4244-2226-5/08/$25.00 ©2008 IEEE